AT88RF256-13-EK Atmel, AT88RF256-13-EK Datasheet - Page 4

• Manufacturer Part Number: AT88RF256-13-EK
• Manufacturer: Atmel

Specifications of AT88RF256-13-EK

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Passwords
Data Locking
Multiple Tags
Data Communications
4
AT88RF256-13
If the optional password mode is enabled with PW_ON, command-based Reads and
Writes are prohibited until the correct password is sent using the Check Password com-
mand. If the transmitted value of the password is correct, then an internal latch is set
and subsequent Read, Write and Lock commands (to any page, including the password
page, #9) are permitted. If the wrong password is sent (to the password check), then the
command is aborted, and the IC reverts to the normal power-up sequence. Writes to
locked pages are never permitted regardless of passwords.
There is no command that can be used to directly read the password page, regardless
of whether or not the password option (PW_ON) is enabled.
Within the lock byte, each lock bit determines whether the corresponding 4-byte user
page can be written to. If it is a “1”, then Writes are prohibited; if “0”, they are allowed.
The data sent to the IC with the Write Lock operation is OR’ed with the data already in
the lock byte and then rewritten to the EEPROM. Once a user page is locked, it may
never be unlocked and may never be written to.
There are two additional lock bits for pages 8 (CONFIG_LOCK) and 9 (PW_LOCK).
They operate slightly differently from the user lock bits because there is no OR function.
CONFIG_LOCK, if “1”, prevents the execution of the Write Config Bits command, while
PW_LOCK, if “1”, prevents execution of the Write Password command. Turning on
CONFIG_LOCK does not lock the value of the bits within the lock byte but does prevent
further change to the PW_LOCK bit and the configuration page.
In order to support multiple tags within the field at the same time, a random delay time
between ID transmissions can be enabled. This feature is implemented by having the IC
randomly disable its activity (transmission of ID frame and enabling the listening win-
dow) at selected times. Commands are only honored during a listening window
immediately following a frame transmission.
The IC includes a random generator that will generate different sequences of enable-
ment/disablement based on processing, voltage, temperature and power-up time.
Depending on the value of the RANDOM option, the transmission of an ID frame will be
enabled on average once in eight times. The maximum delay is twice the average, while
at the minimum, two ID frames/listening windows may be issued back-to-back.
To implement this feature, the tags must be programmed with error detection informa-
tion within the ID field so that the reader can detect the condition when two tags transmit
their ID at exactly the same time. Because of the random delay feature, in most cases
the next transmissions for these two ICs will not overlap.
The Chip Disable command can be used with the random delay feature to permit an
increased number of tags to be identified. Once a tag has been properly read by the
reader unit, the reader sends the Chip Disable command to the tag during the first listen-
ing window after the ID transmission. Until the power is removed, that tag no longer
sends its ID frame.
See the Anticollision Procedures for the AT88RF256-13 Application Note for additional
information on utilizing the anticollision features of the IC.
The electrical signaling of the IC is configurable using configuration bits as in Table 4,
page 12. Options exist to allow compatibility with ISO/IEC 14443-2, “Radio Frequency
Power and Signal Interface” (version N409, Final Committee Draft 3/12/99) Type B
mode. The frame formatting for the various modes of operation is not fully compliant
with ISO/IEC 14443 and is defined below.
1944E–RFID–03/02