HI-8583PQT-10 Holt Integrated Circuits, HI-8583PQT-10 Datasheet - Page 6

• Manufacturer Part Number: HI-8583PQT-10
• Manufacturer: Holt Integrated Circuits

Specifications of HI-8583PQT-10

• Operating Temperature Classification: Military
• Operating Temperature (max): 125C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Not Compliant

FUNCTIONAL DESCRIPTION (cont.)
Once a valid ARINC word is loaded into the FIFO, then EOS
clocks the data ready flag flip flop to a "1",
will go low. The data flag for a receiver will remain low until
ARINC bytes from that receiver are retrieved and the FIFO is
empty. This is accomplished by first activating
byte selector, low to retrieve the first byte and then activating
with SEL high to retrieve the second byte.
from receiver 1 and
Up to 32 ARINC words may be loaded into each receiver’s FIFO.
The
Failure to retrieve data from a full FIFO will cause the next valid
ARINC word received to overwrite the existing data in FIFO
location 32. A FIFO half full flag
contains 16 or more received ARINC words. The
intended to act as an interrupt flag to the system’s external
microprocessor, allowing a 16 word data retrieval routine to be
performed, without the user needing to continually poll the
HI-8582/HI-8583 status register bits.
LABEL RECOGNITION
The chip compares the incoming label to the stored labels if label
recognition is enabled. If a match is found, the data is processed.
If a match is not found, no indicators of receiving ARINC data are
presented. Note that 00(Hex) is treated in the same way as any
other label value. Label bit significance is not changed by the
status of control register bit CR15. Label bits BD00 - BD07 are
always compared to received ARINC bits 1 - 8 respectively.
LOADING LABELS
data (
label memory from the BD00 - BD07 pins. The
write label data for receiver 1 and
ARINC word reception is suspended during the label memory
write sequence.
After a write that takes CR1 from 0 to 1, the next 16 writes of
FF1 FF2
PL
(
pulsed low) load label data into each location of the
) pin will go low when the receiver 1 (2) FIFO is full.
LOAD SHIFT REGISTER
32 BIT PARALLEL
EN2
32 x 32 FIFO
DATA BUS
retrieves data from receiver 2.
HF1 HF2
PL2
(
for receiver 2.
FIGURE 3.
D/R1
) goes low if the FIFO
EN1
PL1
EN
or
HF1 HF2
LOAD
HOLT INTEGRATED CIRCUITS
BIT CLOCK
D/R2
retrieves data
ADDRESS
with SEL, the
pin is used to
WORD CLOCK
(
TRANSMITTER BLOCK DIAGRAM
Note that
(or both)
HI-8582, HI-8583
) pin is
both
EN
GENERATOR
CR4,12
PARITY
6
CR13
CLOCK
DATA
READING LABELS
After the write that changes CR1 from 0 to 1, the next 16 data
reads of the selected receiver (
used to read labels for receiver 1, and
receiver 2. Label data is presented on BD0-BD7.
When writing to, or reading from the label memory, SEL must be a
one, all 16 locations should be accessed, and CR1 must be
written to zero before returning to normal operation. Label
recognition must be disabled (CR2/3=0) during the label read
sequence.
TRANSMITTER
FIFO OPERATION
The FIFO is loaded sequentially by first pulsing
and then
the 31 bit word (or 32 bit word if CR4=0) in the next available
position of the FIFO. If TX/R, the transmitter ready flag is high
(FIFO empty), then up to 32 words, each 31 or 32 bits long, may
be loaded. If TX/R is low, then only the available positions may be
loaded. If all 32 positions are full, the
FIFO ignores further attempts to load data.
A transmitter FIFO half-full flag
transmit FIFO contains less than 16 words,
indicating to the system microprocessor that a 16 ARINC word
block write sequence can be initiated.
In normal operation (CR4=1), the 32nd bit transmitted is a parity
bit. Odd or even parity is selected by programming control
register bit CR12 to a zero or one. If CR4 is programmed to a 0,
then all 32-bits of data loaded into the transmitter FIFO are
treated as data and are transmitted.
SEQUENCER
NULL TIMER
DATA AND
PL2
WORD COUNTER
FIFO CONTROL
DATA CLOCK
SEQUENCER
WORD GAP
COUNTER
LOADING
DIVIDER
to load byte 2. The control logic automatically loads
AND
FIFO
AND
BIT
SEQUENCE
WORD COUNT
INCREMENT
START
LINE DRIVER
EN
HFT
taken low) are labels.
FFT
is provided. When the
TXAOUT
TXBOUT
EN2
flag is asserted and the
TEST
TX CLK
CLK
TX/R
HFT
FFT
ENTX
PL1
PL2
to read labels for
PL1
HFT
to load byte 1
is high,
EN1
is