HI-8583 Holt Integrated Circuits, HI-8583 Datasheet

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HI-8583

Manufacturer Part Number
HI-8583
Description
(HI-8582 / HI-8583) ARINC 429 SYSTEM ON A CHIP
Manufacturer
Holt Integrated Circuits
Datasheet
GENERAL DESCRIPTION
The HI-8582 from Holt Integrated Circuits is a silicon gate
CMOS device for interfacing a 16-bit parallel data bus
directly to the ARINC 429 serial bus. The HI-8582 design
offers many enhancements to the industry standard HI-
8282 architecture. The device provides two receivers each
with label recognition, 32 by 32 FIFO, and analog line
receiver. Up to 16 labels may be programmed for each
receiver. The independent transmitter has a 32 by 32 FIFO
and a built-in line driver. The status of all three FIFOs can
be monitored using the external status pins, or by polling
the HI-8582’s status register. Other new features include a
programmable option of data or parity in the 32nd bit, and
the ability to unscramble the 32 bit word. Also, versions
are available with different values of input resistance and
output resistance to allow users to more easily add external
lightning protection circuitry. The device can be used at
nonstandard data rates when an option pin,
invoked.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The databus, and all control
signals are CMOS and TTL compatible.
The HI-8582 applies the ARINC protocol to the receivers
and transmitter. Timing is based on a 1 Megahertz clock.
Although the line driver shares a common substrate with
the receivers, the design of the physical isolation does not
allow parasitic crosstalk, and thereby achieves the same
isolation as common hybrid layouts.
APPLICATIONS
(DS8582 Rev. H)
June 2001
!
!
!
Avionics data communication
Serial to parallel conversion
Parallel to serial conversion
HOLT INTEGRATED CIRCUITS
NFD
, is
HI-8582, HI-8583
1
FEATURES
PIN CONFIGURATION
BD15 - 9
BD14 - 10
BD12 - 12
BD13 - 11
BD11 - 13
D/R2
SEL - 6
EN1
EN2
HF1
HF2
FF1
FF2
!
!
!
!
!
!
!
!
!
!
!
!
!
ARINC 429 System on a Chip
- 1
- 2
- 3
- 4
- 5
- 7
- 8
ARINC specification 429 compatible
Dual receiver and transmitter interface
Analog line driver and receivers connect
directly to ARINC bus
Programmable label recognition
On-chip 16 label memory for each receiver
32 x 32 FIFOs each receiver and transmitter
Independent data rate selection for
transmitter and each receiver
Status register
Data scramble control
32nd transmit bit can be data or parity
Self test mode
Low power
Industrial & full military temperature ranges
52 - Pin Plastic Quad Flat Pack (PQFP)
(See page 14 for additional pin configuration)
HI-8582PQT
HI-8582PQI
&
(Top View)
39 - N/C
38 -
37 - ENTX
36 - V+
35 - TXBOUT
34 - TXAOUT
33 - V-
32 -
31 -
30 - TX/R
29 -
28 -
27 - BD00
CWSTR
FFT
HFT
PL2
PL1
06/01

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HI-8583 Summary of contents

Page 1

... APPLICATIONS Avionics data communication ! Serial to parallel conversion ! Parallel to serial conversion ! (DS8582 Rev. H) HI-8582, HI-8583 ARINC 429 System on a Chip FEATURES ARINC specification 429 compatible ! Dual receiver and transmitter interface ! Analog line driver and receivers connect ! directly to ARINC bus ...

Page 2

... INPUT NFD INPUT CLK INPUT TX CLK OUTPUT MR INPUT TEST INPUT HI-8582, HI-8583 DESCRIPTION +5V ± ARINC receiver 1 positive input ARINC receiver 1 negative input ARINC receiver 2 positive input ARINC receiver 2 negative input Receiver 1 data ready flag FIFO full Receiver 1 FIFO Half full, Receiver 1 ...

Page 3

... Data 0 Scramble ARINC data format 1 Unscramble ARINC data HI-8582, HI-8583 STATUS REGISTER The HI-8582 contains a 9-bit status interrogated to determine the status of the ARINC receivers, data FIFOs and transmitter. The contents of the status register are output is pulsed low. The control on BD00 - BD08 when the RSR bits are output as zeros ...

Page 4

... Volts to -2.5 Volts ZERO -6.5 Volts to -13 Volts FIGURE 1. ARINC RECEIVER INPUT HI-8582, HI-8583 The HI-8582 guarantees recognition of these levels with a common mode Voltage with respect to GND less than ±5V for the worst case condition (4.75V supply and 13V signal level). The tolerances in the design guarantee detection of the above levels, so the actual acceptance ranges are slightly larger ...

Page 5

... D/R FIFO LOAD CONTROL / LABEL / CONTROL DECODE BIT COMPARE LABEL MEMORY EOS ONES SHIFT REGISTER NULL SHIFT REGISTER ZEROS SHIFT REGISTER HI-8582, HI-8583 CR2(3) ARINC word CR6(9) ARINC word matches label Yes Yes Yes TO PINS CONTROL ...

Page 6

... BD0-7 pins. The PL1 pin is used to write label data for receiver 1 and PL2 for receiver 2. reception is suspended during the label memory write sequence. HI-8582, HI-8583 READING LABELS D/R1 or D/R2 (or both) both After the write that changes CR1 from the next 16 data ...

Page 7

... Clocks The HI-8582 has 37.5 ohms in series with each line driver output. 40 Clocks 320 Clocks The 8583 has 10 ohms in series. The HI-8583 is for applications where external series resistance is needed, typically for lightning protection devices. REPEATER OPERATION Repeater mode of operation allows a data word that has been received by the HI-8582 to be placed directly into the transmitter FIFO ...

Page 8

... TXAOUT ARINC BIT TXBOUT DATA NULL DATA BIT 30 t D/R DATA BUS t ENDATA DATA BUS PL1 PL2 TX/R, HFT FFT , DATA BUS CWSTR HI-8582, HI-8583 DATA NULL NULL BIT 32 BIT SELEN t SELEN ENSEL t t ENEN D/REN t DATAEN t ENDATA BYTE 1 VALID t DWSET t DWHLD ...

Page 9

... DATA BUS DATA BUS t CWSTR t CWHLD t CWSET DATA BUS t DWSET CWSTR t CWHLD t CWSET DATA BUS Set CR1=1 Label #1 t ENDATA HI-8582, HI-8583 t SELEN t ENDATA t SELEN t ENDATA t DWHLD t LABEL t READEN t DATAEN Label #2 HOLT INTEGRATED CIRCUITS 9 t ENSEL t DATAEN t ENSEL t DATAEN Label #16 ...

Page 10

... TXBOUT) 10 one level BIT 32 RIN D D/R D/REN SELEN SEL DON'T CARE t ENPL PL1 PL2 TXR ENTX TXAOUT TXBOUT HI-8582, HI-8583 ARINC BIT ARINC BIT DATA DATA BIT 2 BIT 1 +5V -5V +5V - +10V 90 10% 90% zero level -10V t END ...

Page 11

... Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. HI-8582, HI-8583 Power Dissipation at 25°C Plastic Quad Flat Pack ..................1.5 W, derate 10mW/ C Ceramic J-LEAD CERQUAD ...... 1.0 W, derate 7mW/ DC Current Drain per pin .............................................. ± ...

Page 12

... Logic "1" Output Voltage Logic "0" Output Voltage Output Current: (All Outputs & Bi-directional Pins) Output Capacitance: Operating Voltage Range Operating Supply Current VDD V+ V- HI-8582, HI-8583 SYMBOL CONDITIONS ONE V Pins Common IH ZERO V mode voltage less than ±5V ...

Page 13

... Delay - ENTX HIGH to TXAOUT or TXBOUT: Low Speed Line driver transition differential times: (High Speed, control register CR13 = Logic 0) REPEATER OPERATION TIMING Delay - TX/R LOW to ENTX HIGH Master Reset Pulse Width ARINC Data Rate and Bit Timing HI-8582, HI-8583 + SYMBOL Pulse Width - CWSTR t CWSTR ...

Page 14

... HI-8582CJT EN2 -15 BD15 - 16 BD14 - 17 BD13 - 18 BD12 - 19 BD11 - Pin Cerquad J-lead (See page 1 for additional pin configuration) ORDERING INFORMATION HI - 8582 dash number -10 8582 8583 HI-8582, HI-8583 CWSTR 44 - ENTX TXBOUT 41 - TXAOUT & FFT 38 - HET PL2 ...

Page 15

... J-LEAD CERQUAD 7 8 .040 (1.02 .019 .002 (.483 .051) 52-PIN PLASTIC QUAD FLAT PACK (PQFP) .520 .010 (13.2 .25) SQ. .063 (1.6 See Detail A .092 .004 (2.32 .12) HI-8582 PACKAGE DIMENSIONS .788 (20.0) MAX. SQ. .750 .007 (19.05 .18) .190 MAX. (4.826) .050 TYP. (1.27) .394 .004 SQ. (10.00 .10) .032 .175) Typ ...

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