MT41J128M8JP-125:G Micron Technology Inc, MT41J128M8JP-125:G Datasheet - Page 38

• Manufacturer Part Number: MT41J128M8JP-125:G
• Description: IC DDR3 SDRAM 1GBIT 78FBGA
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT41J128M8JP-125:G

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (128M x 8)
• Speed: 800MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 17:
Table 18:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
I
Speed Bin
CKE
External clock
t
t
t
t
t
t
CL
AL
CS#
Command inputs
Row/column addresses
Bank addresses
Data I/O
Output buffer DQ, DQS
ODT
Burst length
Active banks
Idle banks
DDR3-800
(-25, -25E)
DDR3-1066
(-187, -187E)
DDR3-1333
(-15, -15E, -15F)
DDR3-1600
(-125E, -125F, -125)
DD
CK
RC
RAS
RCD
RRD
RC
Test
I
I
DD
DD
7 Patterns
Measurement Conditions for I
Notes:
Width I
x4, x8 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7
x4, x8 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D
x4, x8 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D
x4, x8 A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D D D A4 RA4 D D D A5 RA5 D D
x16
x16
x16
x16
1. A0 = ACTIVATE bank 0; RA0 = READ with auto precharge bank 0; D = DESELECT.
D D A0 . . .
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D
A7 RA7 D D D D D D A0 . . .
A7 RA7 D D D D D D A0 . . .
A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D A4 RA4 D D D D A5
RA5 D D D D A6 RA6 D D D D A7 RA7 D D D D D D D A0 . . .
A7 RA7 D D D D D D A0 . . .
A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D D D D D D D D D A4 RA4 D D D
A5 RA5 D D D A6 RA6 D D D A7 RA7 D D D D D D D D D D D D D A0 . . .
D A6 RA6 D D D A7 RA7 D D D D D D D A0 . . .
A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D D D D D D A4 RA4 D
D D D A5 RA5 D D D D A6 RA6 D D D D A7 RA7 D D D D D D D D D D D D A0 . . .
I
HIGH
On
t
t
t
t
t
n/a
CL I
CL - 1
HIGH between valid commands
See Table 10 on page 29 for patterns
Stable during DESELECTs (DES)
Looping (see Table 10 on page 29 for patterns)
Read data (BL8): output data switches after every clock cycle, which means that read data is
stable during falling DQS; I/O should be floating when no read data is being driven
Off
Disabled
8 fixed (via MR0)
All, rotational
n/a
DD
DD
CK (MIN) I
RC (MIN) I
RAS (MIN) I
RCD (MIN) I
RRD (MIN) I
7 Pattern
7: All Banks Interleaved Read Current
DD
Electrical Specifications – I
DD
DD
DD
DD
DD
DD
7
38
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
1Gb: x4, x8, x16 DDR3 SDRAM
Specifications and Conditions
©2006 Micron Technology, Inc. All rights reserved.