MT41J64M16LA-15E IT:B Micron Technology Inc, MT41J64M16LA-15E IT:B Datasheet - Page 203
![no-image](/images/manufacturer_photos/0/4/441/micron_technology_inc_sml.jpg)
MT41J64M16LA-15E IT:B
Manufacturer Part Number
MT41J64M16LA-15E IT:B
Description
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Datasheet
1.MT41J64M16LA-15E_ITB.pdf
(208 pages)
Specifications of MT41J64M16LA-15E IT:B
Organization
64Mx16
Density
1Gb
Address Bus
16b
Maximum Clock Rate
1.333GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
-40C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
355mA
Pin Count
96
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Compliant
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Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN
The DRAM’s ODT may exhibit either asynchronous or synchronous behavior during
power-down exit (PDX). This transition period occurs if the DLL is selected to be off
when in precharge power-down mode by setting MR0[12] to 0. Power-down exit begins
t
registered HIGH.
The transition period is
ODT assertion during power-down exit results in an R
t
(MAX) and ODTL on ×
may result in an R
t
Table 88 (page 202) summarizes these parameters.
If the AL has a large value, the uncertainty of the R
because ODTL on and ODTL off are derived from the WL, and WL is equal to CWL + AL.
Figure 120 (page 204) shows three different cases:
• ODT C: asynchronous behavior before
• ODT B: ODT state changes during the transition period, with
• ODT A: ODT state changes after the transition period with synchronous response
ANPD prior to CKE first being registered HIGH, and it ends
AONPD (MIN) and ODTL on ×
AOF (MIN) or as late as the greater of
ODTL off ×
(MAX)
Asynchronous to Synchronous ODT Mode Transition (Power-
t
CK +
t
TT
ANPD is equal to the greater of ODTL off + 1
t
AOF (MIN) and ODTL off ×
change as early as the lesser of
t
CK +
t
ANPD plus
t
203
AON (MAX). ODT deassertion during power-down exit
t
CK +
t
XPDLL.
t
AON (MIN) or as late as the greater of
t
AOFPD (MAX) and ODTL off ×
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
ANPD
t
CK +
TT
t
AOFPD (MIN) and ODTL off ×
state becomes quite large. This is
t
AOF (MAX) greater than
TT
change as early as the lesser of
t
XPDLL after CKE is first
© 2006 Micron Technology, Inc. All rights reserved.
t
CK or ODTL on + 1
t
AOFPD (MIN) less than
t
CK +
Down Exit)
t
t
AOF (MAX).
AONPD
t
AOFPD
t
CK.
t
CK +
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