MT41J64M16LA-15E IT:B Micron Technology Inc, MT41J64M16LA-15E IT:B Datasheet - Page 7

• Manufacturer Part Number: MT41J64M16LA-15E IT:B
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J64M16LA-15E IT:B

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: -40C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 355mA
• Pin Count: 96
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Table 51: DDR3-1333 Speed Bins ................................................................................................................... 73
Table 52: DDR3-1600 Speed Bins ................................................................................................................... 74
Table 53: DDR3-1866 Speed Bins ................................................................................................................... 75
Table 54: Electrical Characteristics and AC Operating Conditions ................................................................... 76
Table 55: Electrical Characteristics and AC Operating Conditions for Speed Extensions ................................... 85
Table 56: Command and Address Setup and Hold Values Referenced at 1 V/ns – AC/DC-Based ....................... 95
Table 57: Derating Values for
Table 58: Derating Values for
Table 59: Derating Values for
Table 60: Derating Values for
Table 61: Minimum Required Time
Table 62: Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based .................................. 103
Table 63: Derating Values for
Table 64: Derating Values for
Table 65: Derating Values for
Table 66: Required Time
Table 67: Truth Table – Command ................................................................................................................ 110
Table 68: Truth Table – CKE ......................................................................................................................... 112
Table 69: READ Command Summary ............................................................................................................ 114
Table 70: WRITE Command Summary .......................................................................................................... 114
Table 71: READ Electrical Characteristics, DLL Disable Mode ........................................................................ 120
Table 72: Write Leveling Matrix ..................................................................................................................... 124
Table 73: Burst Order ................................................................................................................................... 133
Table 74: MPR Functional Description of MR3 Bits ........................................................................................ 142
Table 75: MPR Readouts and Burst Order Bit Mapping .................................................................................. 143
Table 76: Self Refresh Temperature and Auto Self Refresh Description ........................................................... 176
Table 77: Self Refresh Mode Summary .......................................................................................................... 176
Table 78: Command to Power-Down Entry Parameters ................................................................................. 177
Table 79: Power-Down Modes ...................................................................................................................... 178
Table 80: Truth Table – ODT (Nominal) ........................................................................................................ 188
Table 81: ODT Parameter ............................................................................................................................. 188
Table 82: Dynamic ODT Specific Parameters ................................................................................................. 189
Table 83: Mode Registers for R
Table 84: Mode Registers for R
Table 85: Timing Diagrams for Dynamic ODT ............................................................................................... 190
Table 86: Synchronous ODT Parameters ....................................................................................................... 195
Table 87: Asynchronous ODT Timing Parameters for All Speed Bins ............................................................... 200
Table 88: ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period .................................. 202
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN
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DS/
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IH – AC175/DC100-Based ........................................................................... 96
IH – AC150/DC100-Based ........................................................................... 96
IH – AC135/DC100-Based ........................................................................... 97
IH – AC125/DC100-Based ........................................................................... 97
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DH – AC175/DC100-Based ....................................................................... 104
DH – AC150/DC100-Based ....................................................................... 104
DH – AC135/DC100-Based ....................................................................... 105
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VAC Above V
............................................................................................................. 190
............................................................................................................. 190
IH(AC)
(Below V
IH(AC)
IL(AC)
for Valid Transition .................................................... 98
7
) for Valid Transition ............................................. 105
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb: x4, x8, x16 DDR3 SDRAM
© 2006 Micron Technology, Inc. All rights reserved.