TSOP32438SS1F Vishay, TSOP32438SS1F Datasheet - Page 10

• Manufacturer Part Number: TSOP32438SS1F
• Manufacturer: Vishay

Specifications of TSOP32438SS1F

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Si9122
Vishay Siliconix
Care needs to be taken if there is a delay prior to the external
circuit feeding back to the V
power dissipation within the IC it is advisable to use an
external PNP device. A pin has been incorporated on the IC,
(REG_COMP) to provide compensation when employing the
external device. In this case the V
base of the PNP device and controls the current, while the
REG_COMP pin determines the frequency compensation of
the circuit. The value of the REG_COMP capacitor cannot be
too big, otherwise it will slow down the response of the
pre-regulator in the case that fault situations occur and
pre-regulator needs to be turned on again. To understand
the operation please refer to Figure 5.
The soft-start circuit is designed for the dc-dc converter to
start-up in an orderly manner and reduce component stress
on the IC. This feature is programmable by selecting an
external C
from 0 V to the final clamped voltage of 8 V. In the event of
UVLO or shutdown, V
driver switching. To prevent oscillations, a longer soft-start
time may be needed for high capacitive loads and high peak
output current applications.
Reference
The reference voltage of Si9122 is set at 3.3 V. The
reference voltage is de-coupled externally with 0.1 µF
capacitor. The V
has 50 mA source capability.
Voltage Mode PWM Operation
Under normal load conditions, the IC operates in voltage
mode and generates a fixed frequency pulse width
modulated signal to the drivers. Duty cycle is controlled over
a wide range to maintain output voltage under line and load
variation. Voltage feed forward is also included to take
account of variations in supply voltage V
In the half-bridge topology requiring isolation between output
and input, the reference voltage and error amplifier must be
supplied externally, usually on the secondary side. The error
information is thus passed to the power controller through an
opto-coupling device. This information is inverted, hence 0 V
represents the maximum duty cycle, whilst 2 V represents
minimum duty cycle. The error information enters the IC via
pin EP, and is passed to the PWM generator via an inverting
amplifier. The relationship between Duty cycle and V
shown in the Typical Characteristic Graph, Duty Cycle vs.
V
taking the attenuated V
modulating the duty cycle. The relationship between Duty
cycle and V
Graph, Duty Cycle vs. V
At start-up, i.e., once V
initiated under soft-start control which increases primary
switch on-times linearly from D
period. Start-up from a V
under soft-start control.
www.vishay.com
10
EP
25 °C , page 12. Voltage feedforward is implemented by
SS
. An internal 20 µA current source charges C
INDET
REF
is shown in the Typical Characteristic
voltage is 0 V in shutdown mode and
SS
CC
INDET
INDET
IN
will be held low (< 1 V) disabling
is greater than V
CC
signal at V
, page 16.
MIN
supply. To prevent excessive
power down is also initiated
to D
IN
pin is connected to the
MAX
IN
INDET
.
UVLO
over the soft-start
, switching is
and directly
EP
SS
is
Half-Bridge and Synchronous Rectification Timing
Sequence
The PWM signal generated within the Si9122 controls the
low and high-side bridge drivers on alternative cycles. A
period of inactivity always results after initiation of the soft-
start cycle until the soft-start voltage reaches approximately
1.2 V and PWM controlled switching begins. The first bridge
driver to switch is always the low-side, D
charging of the high-side boost capacitor.
The timing and coordination of the drives to the primary and
secondary stages is very important and shown in Figure 3. It
is essential to avoid the situation where both of the
secondary MOSFETs are on when either the high or the low-
side switch are active. In this situation the transformer would
effectively be presented with a short across the output. To
avoid this, a dedicated break-before-make circuit is included
which will generate non overlapping waveforms for the
primary and the secondary drive signals. This is achieved by
a programmable timer which delays the switching on of the
primary driver relative to the switching off of the related
secondary and subsequently delays the switching on of the
secondary relative to the switching off of the related primary.
Typical variation in the t
is shown in graphs t
is due to a reduction in propagation delay through the high-
side driver path as the L
considered in setting the delay for the system level design.
Variation of BBM time with R
t
Primary High- and Low-Side MOSFET Drivers
The drive voltage for the low-side MOSFET switch is
provided directly from V
requires the gate voltage to be enhanced above V
achieved by bootstraping the V
voltage (the high-side MOSFET source). In order to provide
the bootstrapping an external diode and capacitor are
required as shown on the application schematic. The
capacitor will charge up after the low-side driver has turned
on. The switch gate drive signals D
Figure 3.
Secondary MOSFET Drivers
The secondary side MOSFETs are driven from the Si9122
via a center tapped pulse transformer and inverter drivers.
The waveforms from the IC SRH and SRL are shown in
Figure 3. Of importance is the relative voltage between SRH
and SRL, i.e. that which is presented across the primary of
the pulse transformer. When both potentials of SRL and SRH
are equal then by the action of the inverting driver both
secondary MOSFETs are left on.
Oscillator
The oscillator is designed to operate at a nominal frequency
of 500 kHz. The 500 kHz operating frequency allows the
converter to minimize the inductor and capacitor size,
improving the power density of the converter. The oscillator
and therefore the switching frequency is programmable by
attaching a resistor to the R
BBM4
vs. R
BBM
.
BBM3
BBM3
CC
, t
X
. The high-side MOSFET however
BBM4
voltage increases and must be
and t
BBM
and for R
OSC
is shown in graph t
BBM4
CC
S-80038-Rev. J, 14-Jan-08
Document Number: 71815
H
pin. Under overload
voltage onto the L
and D
delay with L
BBM
L
L
as this allows
= 33 kΩ. This
are shown in
IN
X
. This is
BBM1
voltage
to
X