MC9S12DP512CPVE Freescale, MC9S12DP512CPVE Datasheet - Page 105

• Manufacturer Part Number: MC9S12DP512CPVE
• Manufacturer: Freescale

Specifications of MC9S12DP512CPVE

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 14KB
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.25V
• Operating Supply Voltage (min): 2.35/4.5V
• On-chip Adc: 2(8-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

A.5 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).
A.5.1 Startup
Table A-14 summarizes several startup characteristics explained in this section. Detailed description of
the startup behavior can be found in the Clock and Reset Generator (CRG) Block Guide.
A.5.1.1 POR
The release level V
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t
clock. The fastest startup time possible is given by n
A.5.1.2 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.
A.5.1.3 External Reset
When external reset is asserted for a time greater than PW
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
A.5.1.4 Stop Recovery
Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR
is performed before releasing the clocks to the system.
Conditions are shown in Table A-4 unless otherwise noted
Num C
1
2
3
4
5
6
D Reset input pulse width, minimum input time
D Startup from Reset
D Interrupt pulse width, IRQ edge-sensitive mode
D Wait recovery startup time
T POR release level
T POR assert level
PORR
and the assert level V
CQOUT
Rating
Table A-14 Startup Characteristics
no valid oscillation is detected, the MCU will start using the internal self
PORA
are derived from the V
uposc
Symbol
PW
PW
V
V
n
t
.
PORR
PORA
WRS
RST
RSTL
RSTL
IRQ
the CRG module generates an internal
Min
0.97
192
20
2
-
-
MC9S12DP512 Device Guide V01.25
DD
Supply. They are also valid
Typ
-
-
-
-
-
-
Max
2.07
196
14
-
-
-
Unit
n
t
t
osc
ns
cyc
osc
V
V
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