ADSP-BF592KCPZ Analog Devices Inc, ADSP-BF592KCPZ Datasheet - Page 3

• Manufacturer Part Number: ADSP-BF592KCPZ
• Description: 58T4522
• Manufacturer: Analog Devices Inc

Specifications of ADSP-BF592KCPZ

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Rohs Compliant: YES
• Frequency: 400MHz
• Embedded Interface Type: PPI, SPI, UART
• No. Of I/o's: 32
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 64
• Core Supply Voltage: 1.4V
• Lead Free Status / RoHS Status: Compliant

Preliminary Technical Data
GENERAL DESCRIPTION
The ADSP-BF592 processor is a member of the Blackfin
of products, incorporating the Analog Devices/Intel Micro
Signal Architecture (MSA). Blackfin processors combine a dual-
MAC state-of-the-art signal processing engine, the advantages
of a clean, orthogonal RISC-like microprocessor instruction set,
and single-instruction, multiple-data (SIMD) multimedia capa-
bilities into a single instruction-set architecture.
The ADSP-BF592 processor is completely code compatible with
other Blackfin processors. ADSP-BF592 processors offer perfor-
mance up to 400 MHz and reduced static power consumption.
The processor features are shown in
Table 1. Processor Features
1
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next-generation applications that require RISC-like program-
mability, multimedia support, and leading-edge signal
processing in one integrated package.
PORTABLE LOW-POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance. They are produced with a low-power and
low-voltage design methodology and feature on-chip dynamic
power management, which provides the ability to vary both the
voltage and frequency of operation to significantly lower overall
power consumption. This capability can result in a substantial
reduction in power consumption, compared with just varying
the frequency of operation. This allows longer battery life for
portable appliances.
Feature
Timer/Counters with PWM
SPORTs
SPIs
UART
Parallel Peripheral Interface
TWI
GPIOs
Maximum Instruction Rate
Maximum System Clock Speed
Package Options
Maximum instruction rate is not available with every possible SCLK selection.
L1 Instruction SRAM
L1 Instruction ROM
L1 Data SRAM
L1 Scratchpad SRAM
L3 Boot ROM
1
Table
1.
64-Lead LFCSP
ADSP-BF592
400 MHz
100 MHz
Rev. PrC | Page 3 of 46 | August 2010
32K
64K
32K
4K
4K
32
3
2
2
1
1
1
®
family
SYSTEM INTEGRATION
The ADSP-BF592 processor is a highly integrated system-on-a-
chip solution for the next generation of digital communication
and consumer multimedia applications. By combining indus-
try-standard interfaces with a high-performance signal
processing core, cost-effective applications can be developed
quickly, without the need for costly external components. The
system peripherals include a watchdog timer; three 32-bit tim-
ers/counters with PWM support; two dual-channel, full-duplex
synchronous serial ports (SPORTs); two serial peripheral inter-
face (SPI) compatible ports; one UART
parallel peripheral interface (PPI); and a two-wire interface
(TWI) controller.
PROCESSOR PERIPHERALS
The ADSP-BF592 processor contains a rich set of peripherals
connected to the core via several high-bandwidth buses, provid-
ing flexibility in system configuration as well as excellent overall
system performance (see
dedicated communication modules and high-speed serial and
parallel ports, an interrupt controller for flexible management
of interrupts from the on-chip peripherals or external sources,
and power management control functions to tailor the perfor-
mance and power characteristics of the processor and system to
many application scenarios.
The SPORTs, SPIs, UART, and PPI peripherals are supported
by a flexible DMA structure. There are also separate memory
DMA channels dedicated to data transfers between the proces-
sor’s various memory spaces, including boot ROM. Multiple
on-chip buses running at up to 100 MHz provide enough band-
width to keep the processor core running along with activity on
all of the on-chip and external peripherals.
The ADSP-BF592 processor includes an interface to an off-chip
voltage regulator in support of the processor’s dynamic power
management capability.
BLACKFIN PROCESSOR CORE
As shown in
16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,
four video ALUs, and a 40-bit shifter. The computation units
process 8-, 16-, or 32-bit data from the register file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation
are supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and
Figure
2, the Blackfin processor core contains two
Figure
1). The processor also contain
®
with IrDA support; a
ADSP-BF592