NE567D NXP Semiconductors, NE567D Datasheet - Page 12

• Manufacturer Part Number: NE567D
• Manufacturer: NXP Semiconductors

Specifications of NE567D

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Package Type: SO
• Pin Count: 8
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

impedance level at terminal 2 will require that a larger value of C
used for a given filter cutoff frequency. If more than three 567s are to
Philips Semiconductors
ALTERNATE METHOD OF BANDWIDTH
REDUCTION
Although a large value of C
reduces the loop damping so as to slow the circuit response time.
This may be undesirable. Bandwidth can be reduced by reducing
the loop gain. This scheme will improve damping and permit faster
operation under narrow-band conditions. Note that the reduced
be used, the network of R
resistors connected together. A capacitor between this junction and
ground may be required to shunt high frequency components.
2002 Sep 25
Tone decoder/phase-locked loop
NOTE:
130
Adjust control for symmetry of detection band edges
f
about f
250
200
150
100
O
50
PIN 2
567
0
0
10k
0.5k 0.9k 1.4k 1.9k
(Figure 22)
O
.
R
Figure 22. BW reduction
2
DETECTION BAND — % OF f
R
50k
R
B
4
C
A
2
2
and R
will reduce the bandwidth, it also
C 2
6
V+
C
8
can be eliminated and the R
R
R
OPTIONAL SILICON
DIODES FOR
TEMPERATURE
COMPENSATION
1300
2.5k 3.2k 4.0k
f
B
C
R
O
10
10k
R
A
12
R
100k
10k
O
20k
R
R
14
R B
R B R
SL00559
16
C
R
C
A
2
be
12
provide a feedback resistor around the output stage (between Pins 8
For precision very low-frequency applications, where the value of C
OUTPUT LATCHING
To latch the output on after a signal is received, it is necessary to
and 1). Pin 1 is pulled-up to unlatch the output stage.
REDUCTION OF C1 VALUE
becomes large, an overall cost savings may be achieved by
inserting a voltage-follower between the R
so as to allow a higher value of R
given frequency.
PROGRAMMING
To change the center frequency, the value of R
with a mechanical or solid state switch, or additional C
may be added by grounding them through saturating NPN
transistors.
NOTE:
C
A
prevents latch-up when power supply is turned on.
UNLATCH
UNLATCH
Figure 23. Output latching
10k
R
A
V+
V+
(Figure 23)
C
A
567 8
1
1
567 8
and a lower value of C
1
C
C
3
3
R
20k
NE567/SE567
f
R
20k
1
SL00560
f
V+
C
V+
R
1
R
L
1
junction and Pin 6,
L
can be changed
1
capacitors
Product data
1
for a
1