LFXP6C-4F256I LATTICE SEMICONDUCTOR, LFXP6C-4F256I Datasheet - Page 16

• Manufacturer Part Number: LFXP6C-4F256I
• Description: FPGA LatticeXP Family 6000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 256-Pin FBGA Tray
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFXP6C-4F256I

• Package: 256FBGA
• Family Name: LatticeXP
• Device Logic Units: 6000
• Maximum Internal Frequency: 360 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 188
• Ram Bits: 73728
• Re-programmability Support: Yes

Lattice Semiconductor
Figure 2-14. sysMEM Memory Primitives
The EBR memory supports three forms of write behavior for single port or dual port operation:
1. Normal – data on the output appears only during read cycle. During a write cycle, the data (at the current
2. Write Through -þa copy of the input data appears at the output of the same port during a write cycle.þThis
3. Read-Before-Write – when new data is being written, the old content of the address appears at the output.
Memory Core Reset
The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-
nously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B respec-
tively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated resets for both
ports are as shown in Figure 2-15.
address) does not appear on the output. This mode is supported for all data widths.
mode is supported for all data widths.
This mode is supported for x9, x18 and x36 data widths.
AD[12:0]
AD[12:0]
DI[35:0]
CS[2:0]
CS[2:0]
RST
RST
CLK
CLK
WE
CE
CE
Single Port RAM
ROM
EBR
EBR
DO[35:0]
DO[35:0]
2-13
ADW[12:0]
DOA[17:0]
ADA[12:0]
DIA[17:0]
CSA[2:0]
DI[35:0]
CS[2:0]
CLKW
CLKA
RSTA
CEW
WEA
CEA
RST
WE
Pseudo-Dual Port RAM
True Dual Port RAM
EBR
EBR
LatticeXP Family Data Sheet
ADB[12:0]
DIB[17:0]
CEB
CLKB
RSTB
WEB
CSB[2:0]
DOB[17:0]
ADR[12:0]
DO[35:0]
CER
CLKR
Architecture