LFXP6C-4F256I LATTICE SEMICONDUCTOR, LFXP6C-4F256I Datasheet - Page 19

• Manufacturer Part Number: LFXP6C-4F256I
• Description: FPGA LatticeXP Family 6000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 256-Pin FBGA Tray
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFXP6C-4F256I

• Package: 256FBGA
• Family Name: LatticeXP
• Device Logic Units: 6000
• Maximum Internal Frequency: 360 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 188
• Ram Bits: 73728
• Re-programmability Support: Yes

Lattice Semiconductor
Figure 2-18. Group of Seven PIOs
Figure 2-19. DQS Routing
PIO
The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic
block. These blocks contain registers for both single data rate (SDR) and double data rate (DDR) operation along
with the necessary clock and selection logic. Programmable delay lines used to shift incoming clock and data sig-
nals are also included in these blocks.
Input Register Block
The input register block contains delay elements and registers that can be used to condition signals before they are
passed to the device core. Figure 2-20 shows the diagram of the input register block.
Input signals are fed from the sysIO buffer to the input register block (as signal DI). If desired the input signal can
bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and
Four PICs
DQS
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
2-16
Buffer
sysIO
Delay
Assigned DQS Pin
LatticeXP Family Data Sheet
PADA “T”
PADB “C”
PADA “T”
PADB “C”
PADA “T”
PADB “C”
PADA “T”
PADB “C”
PADA “T”
PADB “C”
PADA “T”
PADB “C”
PADA “T”
PADB “C”
PADB “C”
PADA “T”
PADB “C”
PADA “T”
PADA “T”
PADA “T”
PADB “C”
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
One PIO Pair
Architecture