LCBS-8-01 Richco Plastic Co, LCBS-8-01 Datasheet - Page 2

• Manufacturer Part Number: LCBS-8-01
• Description: LOCKING BOARD SUPPORT 1/2"
• Manufacturer: Richco Plastic Co
• Series: LCBSr

Specifications of LCBS-8-01

• Holding Type: Arrowhead, Snap Lock
• Length: 1.229" (31.22mm)
• Between Board Height: 0.500" (12.70mm) 1/2"
• Mounting Type: Arrowhead, Snap-Lock, Winged
• Support Hole Diameter: 0.156" (3.96mm) 5/32"
• Support Panel Thickness: 0.062" (1.57mm) 1/16"
• Mounting Hole Diameter: 0.187" (4.75mm) 3/16"
• Mounting Panel Thickness: 0.031 ~ 0.078" (0.79 ~ 1.98mm)
• Overall Length: 12.7mm
• Spacer Material: Nylon
• External Width: 7.1mm
• Spacing Height: 12.7mm
• Body Diameter: 4.75mm
• Spacer Style: PC Board
• Color: Natural
• Diameter: 0.28 in.
• Diameter, Mounting Hole: 0.156 in. ±0.003 in. Dia. Hole in a 0.82 in. Thick Board, 0.187 in. ±0.003 in. Dia. Hole in a 1⁄16 in. (Nominal) Thick Panel⁄Chassis
• Size, Thread: 7⁄32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: LCBS-8; RP430

OPERATION
The main elements of the Serial Timekeeper are shown
in Figure 1: shift register, control logic, oscillator, real
time clock, and RAM. To initiate any transfer of data,
RST is taken high and eight bits are loaded into the shift
register providing both address and command informa-
tion. Data is serially input on the rising edge of the SCLK.
The first eight bits specify which of 32 bytes will be ac-
cessed, whether a read or write cycle will take place,
and whether a byte or burst mode transfer is to occur.
After the first eight clock cycles have occurred which
load the command word into the shift register, additional
clocks will output data for a read or input data for a write.
DS1202 BLOCK DIAGRAM Figure 1
ADDRESS/COMMAND BYTE Figure 2
DS1202, DS1202S
032697 2/11
I/O
SCLK
RST
INPUT SHIFT
REGISTERS
7
1
RAM
6
CK
A4
5
CONTROL LOGIC
COMMAND AND
REAL TIME
A3
4
CLOCK
DATA BUS
A2
3
The number of clock pulses equals eight plus eight for
byte mode or eight plus up to 192 for burst mode.
COMMAND BYTE
The command byte is shown in Figure 2. Each data
transfer is initiated by a command byte. The MSB (Bit 7)
must be a logic 1. If it is zero, further action will be termi-
nated. Bit 6 specifies clock/calendar data if logic 0 or
RAM data if logic 1. Bits one through five specify the
designated registers to be input or output, and the LSB
(Bit 0) specifies a write operation (input) if logic 0 or read
operation (output) if logic 1. The command byte is al-
ways input starting with the LSB (bit 0).
ADDRESS BUS
A1
2
A0
1
X1
RD
0
AND DIVIDER
OSCILLATOR
24 X 8 RAM
W
32.768 KHz
X2