LCBS-8-01 Richco Plastic Co, LCBS-8-01 Datasheet - Page 3
![LOCKING BOARD SUPPORT 1/2"](/photos/6/34/63418/lcbs-8-01_sml.jpg)
LCBS-8-01
Manufacturer Part Number
LCBS-8-01
Description
LOCKING BOARD SUPPORT 1/2"
Manufacturer
Richco Plastic Co
Series
LCBSr
Specifications of LCBS-8-01
Holding Type
Arrowhead, Snap Lock
Length
1.229" (31.22mm)
Between Board Height
0.500" (12.70mm) 1/2"
Mounting Type
Arrowhead, Snap-Lock, Winged
Support Hole Diameter
0.156" (3.96mm) 5/32"
Support Panel Thickness
0.062" (1.57mm) 1/16"
Mounting Hole Diameter
0.187" (4.75mm) 3/16"
Mounting Panel Thickness
0.031 ~ 0.078" (0.79 ~ 1.98mm)
Overall Length
12.7mm
Spacer Material
Nylon
External Width
7.1mm
Spacing Height
12.7mm
Body Diameter
4.75mm
Spacer Style
PC Board
Color
Natural
Diameter
0.28 in.
Diameter, Mounting Hole
0.156 in. ±0.003 in. Dia. Hole in a 0.82 in. Thick Board, 0.187 in. ±0.003 in. Dia. Hole in a 1⁄16 in. (Nominal) Thick Panel⁄Chassis
Size, Thread
7⁄32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
LCBS-8
RP430
RP430
RESET AND CLOCK CONTROL
All data transfers are initiated by driving the RST input
high. The RST input serves two functions. First, RST
turns on the control logic which allows access to the shift
register for the address/command sequence. Second,
the RST signal provides a method of terminating either
single byte or multiple byte data transfer. A clock cycle is
a sequence of a falling edge followed by a rising edge.
For data inputs, data must be valid during the rising
edge of the clock and data bits are output on t he falling
edge of clock. All data transfer terminates if the RST in-
put is low and the I/O pin goes to a high impedance
state. Data transfer is illustrated in Figure 3.
DATA INPUT
Following the eight SCLK cycles that input a write com-
mand byte, a data byte is input on the rising edge of the
next eight SCLK cycles. Additional SCLK cycles are ig-
nored should they inadvertently occur. Data is input
starting with bit 0. Due to the inherent nature of the logic
state machine, writing times containing an absolute
value of “59” seconds should be avoided.
DATA OUTPUT
Following the eight SCLK cycles that input a read com-
mand byte, a data byte is output on the falling edge of
the next eight SCLK cycles. Note that the first data bit to
be transmitted occurs on the first falling edge after the
last bit of the command byte is written. Additional SCLK
cycles retransmit the data bytes should they inadver-
tently occur so long as RST remains high. This opera-
tion permits continuous burst mode read capability.
Data is output starting with bit 0.
BURST MODE
Burst mode may be specified for either the clock/calen-
dar or the RAM registers by addressing location 31 deci-
mal (address/command bits one through five = logical
one). As before, bit six specified clock or RAM and bit 0
specifies read or write. There is no data storage capac-
ity at locations 8 through 31 in the Clock/Calendar Reg-
isters or locations 24 through 31 in the RAM registers.
When writing to the clock registers in the burst mode,
the first eight registers must be written in order for the
data to be transferred.
However, when writing to RAM in burst mode it is not
necessary to write all 24 bytes for the data to transfer.
Each byte that is written to will be transferred to RAM
regardless of whether all 24 bytes are written or not.
CLOCK/CALENDAR
The clock/calendar is contained in eight write/read reg-
isters as shown in Figure 4. Data contained in the clock/
calendar registers is in binary coded decimal format
(BCD).
CLOCK HALT FLAG
Bit 7 of the seconds register is defined as the clock halt
flag. When this bit is set to logic 1, the clock oscillator is
stopped and the DS1202 is placed into a low–power
standby mode with a current drain of not more than 100
nanoamps. When this bit is written to logic 0, the clock
will start.
AM–PM/12–24 MODE
Bit 7 of the hours register is defined as the 12– or
24–hour mode select bit. When high, the 12–hour mode
is selected. In the 12–hour mode, bit 5 is the AM/PM bit
with logic high being PM. In the 24–hour mode, bit 5 is
the second 10 hour bit (20–23 hours).
WRITE PROTECT BIT
Bit 7 of the control register is the write protect bit. The
first seven bits (bits 0–6) are forced to zero and will al-
ways read a zero when read. Before any write operation
to the clock or RAM, bit 7 must be zero. When high, the
write protect bit prevents a write operation to any other
register.
CLOCK/CALENDAR BURST MODE
The clock/calendar command byte specifies burst
mode operation. In this mode the eight clock/calendar
registers can be consecutively read or written (see Fig-
ure 4) starting with bit 0 of address 0.
RAM
The static RAM is 24 x 8 bytes addressed consecutively
in the RAM address space.
RAM BURST MODE
The RAM command byte specifies burst mode opera-
tion. In this mode, the 24 RAM registers can be consec-
utively read or written (see Figure 4) starting with bit 0 of
address 0.
DS1202, DS1202S
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