HDMP-2634 Avago Technologies US Inc., HDMP-2634 Datasheet - Page 4

• Manufacturer Part Number: HDMP-2634
• Manufacturer: Avago Technologies US Inc.

Specifications of HDMP-2634

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Not Compliant

FRAME MUX
The FRAME MUX accepts 10-bit
wide parallel data from the
INPUT LATCH. Using internally
generated high-speed clocks, this
parallel data is multiplexed into a
2.5 GBd serial data stream. The
data bits are transmitted sequen-
tially from TX[0] to TX[9]. The
leftmost bit of K28.5+ is on
TX[0].
OUTPUT SELECT
The OUTPUT SELECT block
picks the serial data to drive on
to the serial output line. In
normal operation, the serialized
TX[0:9] data is placed at SO . In
parallel loopback (EWRAP=1)
mode, the SO
static at logic 1 and the internal
serial output signal going to the
INPUT SELECT block of the
receiver section is used to gener-
ate RX[0:9]. In addition, the
OUTPUT SELECT block allows
the user to control the amount of
pre-emphasis used on the SO
pins. If pre-emphasis is used,
0 1 and 1 0 transitions on
SO
0 0 and 1 1 transitions. This
increased amplitude is used to
offset the effects of skin loss and
dispersion on long PCB transmis-
sion lines. Pre-emphasis is con-
trolled by the EQAMP pin (Table
2 and Figure 9).
INPUT SELECT
The INPUT SELECT block picks
the serial data that will be
parallelized to drive RX[0:9]. In
normal operation, serial data is
accepted at SI . In parallel
loopback (EWRAP=1) mode, the
internal serial output signal from
the OUTPUT SELECT block of
the transmitter section is used to
generate RX[0:9].
4
have greater amplitude than
pins are held
RX PLL/CLOCK RECOVERY
The Receiver Phase Locked Loop
and Clock Recovery block is re-
sponsible for frequency and
phase locking onto the incoming
serial data stream and recovering
the bit and byte clocks. An auto-
matic locking feature allows the
Rx PLL to lock onto the input
data stream without external PLL
training controls. It does this by
continually frequency locking
onto the 125 MHz reference
clock, and then phase locking
onto the selected input data
stream. An internal signal detec-
tion circuit monitors the presence
of the input and invokes the
phase detection as the data
stream appears. Once bit locked,
the receiver generates the high-
speed sampling clock for the
input sampler.
INPUT SAMPLER
The INPUT SAMPLER is respon-
sible for converting the serial
input signal into a retimed bit
stream. To accomplish this, it
uses the high-speed serial clock
generated from the RX PLL/
CLOCK RECOVERY block. This
serial bit stream is sent to the
FRAME DEMUX AND BYTE
SYNC block.
FRAME DEMUX AND BYTE SYNC
The FRAME DEMUX AND BYTE
SYNC block is responsible for
restoring the 10-bit parallel data
from the high-speed serial bit
stream. This block is also
responsible for recognizing the
first seven bits of the K28.5+
positive disparity comma charac-
ter (0011111xxx). When recog-
nized, the FRAME DEMUX AND
BYTE SYNC block works with the
RX PLL/CLOCK RECOVERY
block to select the proper parallel
data edge out of the bit stream so
that the next comma character
starts at RX[0]. When a comma
character is detected and realign-
ment of the receive byte clock
RBC[0:1] is necessary, these
clocks are stretched (never sliv-
ered) to the next correct align-
ment position. RBC[0:1] will be
aligned by the start of the next
ordered set (two-byte group)
after K28.5+ is detected. The
start of the next ordered set will
be aligned with the rising edge of
RBC[1], independent of the
RX_RATE pin setting. Per the
Fibre Channel encoding scheme,
comma characters must not be
transmitted in consecutive bytes
so that the receive byte clocks
may maintain their proper recov-
ered frequencies.
OUTPUT DRIVERS
The OUTPUT DRIVERS present
the 10-bit parallel recovered data
(RX[0:9]) properly aligned to the
receive byte clock (RBC[0:1]) as
shown in Figures 5a-5d and
Table 1. These output drivers
provide single ended SSTL_2
compatible signals.
RECEIVER LOSS OF SIGNAL
The RECEIVER LOSS OF SIGNAL
block examines the peak-to-peak
differential amplitude at the SI
input. When this amplitude is too
small, RX_LOS is set to 1, and
RX[0:9] are set to logic one
(1111111111). This prevents
generation of random data at
the RX[0:9] pins when the serial
input lines are disconnected.
When the signal at SI
amplitude, RX_LOS is set to
logic 0, and the output of the
INPUT SELECT block is passed
through.
is a valid