5962-87789022A Analog Devices Inc, 5962-87789022A Datasheet - Page 5

• Manufacturer Part Number: 5962-87789022A
• Manufacturer: Analog Devices Inc

Specifications of 5962-87789022A

• Number Of Channels: 1
• Resolution: 8b
• Interface Type: Parallel
• Single Supply Voltage (typ): 5/9/12/15V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: R-2R
• Power Supply Requirement: Single
• Output Type: Voltage
• Single Supply Voltage (min): 4.5V
• Single Supply Voltage (max): 16.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 20
• Settling Time: 3us
• Lead Free Status / RoHS Status: Not Compliant

REV. A
NOTE: Decreasing the scale by putting a resistor in series with GND
will not work properly due to the code-dependent currents in GND.
Adjusting offset by injecting dc at GND is not recommended for the
same reason.
GROUNDING AND BYPASSING*
All precision converter products require careful application of
good grounding practices to maintain full rated performance.
Because the AD558 is intended for application in microcom-
puter systems where digital noise is prevalent, special care must
be taken to assure that its inherent precision is realized.
The AD558 has two ground (common) pins; this minimizes
ground drops and noise in the analog signal path. Figure 5
shows how the ground connections should be made.
It is often advisable to maintain separate analog and digital
grounds throughout a complete system, tying them common in
one place only. If the common tie-point is remote and acciden-
tal disconnection of that one common tie-point occurs due to
card removal with power on, a large differential voltage between
the two commons could develop. To protect devices that inter-
face to both digital and analog parts of the system, such as the
AD558, it is recommended that common ground tie-points
should be provided at each such device. If only one system
ground can be connected directly to the AD558, it is recom-
mended that analog common be selected.
POWER SUPPLY CONSIDERATIONS
The AD558 is designed to operate from a single positive power
supply voltage. Specified performance is achieved for any supply
voltage between +4.5 V and +16.5 V. This makes the AD558
ideal for battery-operated, portable, automotive or digital main-
frame applications.
*For additional insight, “An IC Amplifier Users’ Guide to Decoupling,
Grounding and Making Things Go Right For A change,” is available
at no charge from any Analog Devices Sales Office.
Figure 5. Recommended Grounding and Bypassing
Figure 4. 10.24 V Full-Scale Connection
40k
OUTPUT
2k
AMP
OUTPUT
AMP
14k
14
16
15
13
12
11
V
V
V
GND
GND
+V
16
13
OUT
OUT
OUT
15
14
CC
SELECT
SENSE
500
GND
0.1 F
(SEE NEXT
TO SYSTEM GND
TO SYSTEM GND
TO SYSTEM V
PAGE)
604
(SEE TEXT)
V
OUT
R
CC
L
–5–
The only consideration in selecting a supply voltage is that, in
order to be able to use the 0 V to 10 V output range, the power
supply voltage must be between +11.4 V and +16.5 V. If, how-
ever, the 0 V to 2.56 V range is to be used, power consumption
will be minimized by utilizing the lowest available supply voltage
(above +4.5 V).
TIMING AND CONTROL
The AD558 has data input latches that simplify interface to 8-
and 16-bit data buses. These latches are controlled by Chip
Enable (CE) and Chip Select (CS) inputs. CE and CS are inter-
nally “NORed” so that the latches transmit input data to the
DAC section when both CE and CS are at Logic “0”. If the ap-
plication does not involve a data bus, a “00” condition allows
for direct operation of the DAC. When either CE or CS go to
Logic “1”, the input data is latched into the registers and held
until both CE and CS return to “0”. (Unused CE or CS inputs
should be tied to ground.) The truth table is given in Table I.
The logic function is also shown in Figure 6.
Input Data
0
1
0
1
0
1
X
X
NOTES
X = Does not matter.
g = Logic Threshold at Positive-Going Transition.
In a level-triggered latch such as that in the AD558 there is an
interaction between data setup and hold times and the width of
the enable pulse. In an effort to reduce the time required to test
all possible combinations in production, the AD558 is tested
with t
with t
these specifications may result in data not being latched properly.
Figure 7 shows the timing for the data and control signals; CE
and CS are identical in timing as well as in function.
DS
DH
= t
= 10 ns at all temperatures. Failure to comply with
Table I. AD558 Control Logic Truth Table
Figure 6. AD558 Control Logic Function
W
= 200 ns at 25 C and 270 ns at T
CE
0
0
g
g
0
0
1
X
CS
0
0
0
0
g
g
X
1
Applications–AD558
DAC Data
0
1
0
1
0
1
Previous Data Latched
Previous Data Latched
MIN
Latch
Condition
“Transparent”
“Transparent”
Latching
Latching
Latching
Latching
and T
MAX
,