AD9484BCPZ-500 Analog Devices Inc, AD9484BCPZ-500 Datasheet - Page 8

• Manufacturer Part Number: AD9484BCPZ-500
• Description: IC ADC 8BIT 500MSPS 56LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9484BCPZ-500

• Sampling Rate: 500MSPS
• Input Channel Type: Differential, Single Ended
• Data Interface: Serial, SPI
• Supply Current: 283mA
• Digital Ic Case Style: LFCSP
• No. Of Pins: 56
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Resolution (bits): 8bit
• Number Of Elements: 1
• Resolution: 8Bit
• Architecture: Pipelined
• Input Type: Voltage
• Differential Input: Yes
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 1.8V
• Single Supply Voltage (max): 1.9V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 720mW
• Differential Linearity Error: ±0.25LSB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: LFCSP EP
• Input Signal Type: Differential
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 7. Pin Function Descriptions
Pin No.
0
30, 32 to 34, 37 to 39,
41 to 43, 46
7, 24, 47
8, 23, 48
35
36
40
44
45
31
1, 2, 28, 51 to 56
25
26
27
29
49
50
3
4
5
6
9
10
11
12
13
AD9484
Mnemonic
AGND
AVDD
DRVDD
DRGND
VIN+
VIN−
CML
CLK+
CLK−
VREF
DNC
SDIO
SCLK/DFS
CSB
PWDN
DCO−
DCO+
D0−
D0+
D1−
D1+
D2−
D2+
D3−
D3+
D4−
1
1
DRGND
DRVDD
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. AGND AND DRGND SHOULD BE TIED TO A COMMON
3. THE EXPOSED PADDLE MUST BE SOLDERED TO
DNC
DNC
D0+
D1+
D2+
D3+
D4+
D0–
D1–
D2–
D3–
D4–
QUIET GROUND PLANE.
A GROUND PLANE.
Description
Analog Ground. The exposed paddle must be soldered to a ground plane.
1.8 V Analog Supply.
1.8 V Digital Output Supply.
Digital Output Ground.
Analog Input—True.
Analog Input—Complement.
Common-Mode Output. Enabled through the SPI, this pin provides a reference for the
optimized internal bias voltage for VIN+/VIN−.
Clock Input—True.
Clock Input—Complement.
Voltage Reference Internal/Input/Output. Nominally 0.75 V.
Do Not Connect. Do not connect to this pin. This pin should be left floating.
Serial Port Interface (SPI) Data Input/Output.
Serial Port Interface Clock (Serial Port Mode)/Data Format Select (External Pin Mode).
Serial Port Chip Select (Active Low).
Chip Power-Down.
Data Clock Output—Complement.
Data Clock Output—True.
D0 Complement Output (LSB).
D0 True Output (LSB).
D1 Complement Output.
D1 True Output.
D2 Complement Output.
D2 True Output.
D3 Complement Output.
D3 True Output.
D4 Complement Output.
10
11
12
13
14
1
2
3
4
5
6
7
8
9
PIN 0 (EXPOSED PADDLE) = AGND
PIN 1
INDICATOR
Figure 3. Pin Configuration
Rev. 0 | Page 8 of 24
(Not to Scale)
AD9484
TOP VIEW
42 AVDD
41 AVDD
40 CML
39 AVDD
38 AVDD
37 AVDD
36 VIN–
35 VIN+
34 AVDD
33 AVDD
32 AVDD
31 VREF
30 AVDD
29 PWDN