PIC24FV32KA304-I/PT Microchip Technology, PIC24FV32KA304-I/PT Datasheet - Page 130

• Manufacturer Part Number: PIC24FV32KA304-I/PT
• Description: MCU 32KB FLASH 2KB RAM 44-TQFP
• Manufacturer: Microchip Technology

Specifications of PIC24FV32KA304-I/PT

• Processor Series: PIC24FV
• Core: PIC
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-44
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DSWCKSEL
postscaler
PIC24FV32KA304 FAMILY
10.2.4.5
To enable the DSWDT in Deep Sleep mode, program
the Configuration bit, DSWDTEN (FDS<7>). The
device Watchdog Timer (WDT) need not be enabled for
the DSWDT to function. Entry into Deep Sleep mode
automatically resets the DSWDT.
The DSWDT clock source is selected by the
DSWDTPS<3:0> Configuration bits (FDS<3:0>). The
minimum time-out period that can be achieved is 2.1 ms
and the maximum is 25.7 days. For more details on the
FDS Configuration register and DSWDT configuration
options, refer to
10.2.4.6
Both the RTCC and the DSWDT may run from either
SOSC or the LPRC clock source. This allows both the
RTCC and DSWDT to run without requiring both the
LPRC and SOSC to be enabled together, reducing
power consumption.
Running the RTCC from LPRC will result in a loss of
accuracy in the RTCC of approximately 5 to 10%. If a
more accurate RTCC is required, it must be run from
the SOSC clock source. The RTCC clock source is
selected with the RTCOSC Configuration bit (FDS<5>).
Under certain circumstances, it is possible for the
DSWDT clock source to be off when entering Deep
Sleep mode. In this case, the clock source is turned on
automatically (if DSWDT is enabled), without the need
for software intervention. However, this can cause a
delay in the start of the DSWDT counters. In order to
avoid this delay when using SOSC as a clock source,
the application can activate SOSC prior to entering
Deep Sleep mode.
10.2.4.7
Upon entry into Deep Sleep mode, the status bit,
DPSLP (RCON<10>), becomes set and must be
cleared by the software.
On power-up, the software should read this status bit to
determine if the Reset was due to an exit from Deep
Sleep mode and clear the bit if it is set. Of the four
possible combinations of DPSLP and POR bit states,
three cases can be considered:
• Both the DPSLP and POR bits are cleared. In this
• The DPSLP bit is clear, but the POR bit is set.
• Both the DPSLP and POR bits are set. This
DS39995B-page 130
case, the Reset was due to some event other
than a Deep Sleep mode exit.
This is a normal POR.
means that Deep Sleep mode was entered, the
device was powered down and Deep Sleep mode
was exited.
options
Deep Sleep WDT
Switching Clocks in Deep Sleep
Mode
Checking and Clearing the Status of
Deep Sleep
Configuration
Section 26.0 “Special
are
programmed
bit
(FDS<4>).
Features”.
by
The
the
10.2.4.8
V
exiting from Deep Sleep functionally looks like a POR,
the
“Checking and Clearing the Status of Deep Sleep”
should be used to distinguish between Deep Sleep and
a true POR event.
When a true POR occurs, the entire device, including
all Deep Sleep logic (Deep Sleep registers: RTCC,
DSWDT, etc.) is reset.
10.2.4.9
To review, these are the necessary steps involved in
invoking and exiting Deep Sleep mode:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Device exits Deep Sleep when a wake-up event
11. The DSEN bit is automatically cleared.
12. Read and clear the DPSLP status bit in RCON,
13. Read the DSGPRx registers (optional).
14. Once all state related configurations are
15. Application resumes normal operation.
DD
Device exits Reset and begins to execute its
application code.
If DSWDT functionality is required, program the
appropriate Configuration bit.
Select the appropriate clock(s) for the DSWDT
and RTCC (optional).
Enable and configure the DSWDT (optional).
Enable and configure the RTCC (optional).
Write context data to the DSGPRx registers
(optional).
Enable the INT0 interrupt (optional).
Set the DSEN bit in the DSCON register.
Enter Deep Sleep by issuing a PWRSV
#SLEEP_MODE command.
occurs.
and the DSWAKE status bits.
complete, clear the RELEASE bit.
voltage is monitored to produce PORs. Since
technique
Power-on Resets (
Summary of Deep Sleep Sequence
described
 2011 Microchip Technology Inc.
in
PORs
Section 10.2.4.7
)