ADN2819ACP-CML Analog Devices Inc, ADN2819ACP-CML Datasheet - Page 19

• Manufacturer Part Number: ADN2819ACP-CML
• Description: IC RECOVER CLOCK/DATA 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock and Data Recovery (CDR)r

Specifications of ADN2819ACP-CML

• Rohs Status: RoHS non-compliant
• Output: CML
• Frequency - Max: 2.7GHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 2.7GHz
• Input: -

CHOOSING AC-COUPLING CAPACITORS
The choice of ac-coupling capacitors at the input (PIN, NIN)
and output (DATAOUTP, DATAOUTN) of the ADN2819 must
be chosen such that the device works properly at the lower
OC-3 and higher OC-48 data rates. When choosing the
capacitors, the time constant formed with the two 50 Ω resistors
in the signal path must be considered. When a large number of
consecutive identical digits (CIDs) are applied, the capacitor
voltage can drop due to baseline wander (see Figure 23), causing
pattern dependent jitter (PDJ).
NOTES
1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS 0.
2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE V
3. WHEN THE BURST OF DATA STARTS AGAIN,THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO THE INPUT LEVELS,
4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2819. THE QUANTIZER WILL BE
WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS.
CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES, EITHER HIGH OR LOW DEPENDING ON
THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELLED OUT. THE QUANTIZER WILL NOT RECOGNIZE THIS AS A VALID STATE.
ABLE TO RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT.
V
V1b
V2b
DIFF
V1
V2
VTH = ADN2819 QUANTIZER THRESHOLD
V
DIFF
= V2–V2b
1
TIA
V1b
V1
C
C
IN
IN
2
V2b
V2
NIN
PIN
Figure 25. Example of Baseline Wander
50Ω
50Ω
V
REF
Rev. B | Page 19 of 24
+
LIMAMP
ADN2819
3
For the ADN2819 to work robustly at both OC-3 and OC-48, a
minimum capacitor of 1.6 µF to PIN/NIN and 0.1 µF on
DATAOUTP/DATAOUTN should be used. This is based on the
assumption that 1000 CIDs must be tolerated and that the PDJ
should be limited to 0.01 UI p-p.
CDR
4
C
C
OUT
OUT
DATAOUTP
DATAOUTN
REF
LEVEL,
VTH
V
REF
ADN2819