ICS95V157AGLFT IDT, Integrated Device Technology Inc, ICS95V157AGLFT Datasheet - Page 2

• Manufacturer Part Number: ICS95V157AGLFT
• Description: IC CLK DVR SSTL_2 2.5V 48-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of ICS95V157AGLFT

• Input: Clock
• Output: SSTL-2
• Frequency - Max: 233MHz
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Frequency-max: 233MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 95V157AGLFT

Pin Descriptions
ICS95V157
This PLL Clock Buffer is designed for a V
ICS95V157 is a zero delay buffer that distributes a single-ended clock input (CLK_INT) to ten differential pair of clock
outputs (CLKT[0:9], CLKC[0:9]) and one single-ended feedback clock output (FB_OUTT). The clock outputs are
controlled by the input clocks (CLK_INT), the feedback clock (FB_INT), the 2.5-V LVCMOS input (PD#) and the analog
power input (AV
and the differential clock outputs are tri-stated. When AV
purposes.
The PLL in the ICS95V157 clock driver uses the input clocks (CLK_INT) and the feedback clock (FB_INT) to provide
high-performance, low-skew, low-jitter, output differential clocks (CLKT [0:9], CLKC [0:9]). ICS95V157 is also able to
track Spread Spectrum Clock (SSC) for reduced EMI.
ICS95V157 is characterized for operation from 0°C to 85°C.
0501C—11/24/08
2
2
, 1
, 4
, 7
, 6
2
I P
2
3
2
, 7
, 2
1
, 8
, 1
, 3
2
3
N
1
, 1
, 9
, 0
, 8
2
, 4
3
4
1
N
, 0
1
, 4
, 1
, 9
1
3
4
3
3
3
1
1
1
3
U
, 2
, 9
, 0
, 8
1
2
6
7
6
7
3
, 3
3
, 9
M
4
, 0
1
, 8
, 2
4
4
2
3
B
, 5
, 6
, 4
, 3
, 4
, 5
5
4
E
4
2
, 5
8
2
R
4
4
2
3
DD
, 1
, 5
, 6
, 7
). When input (PD#) is low while power is applied, the receivers are disabled, the PLL is turned off
G
C
C
C
F
F
N
P
V
A
A
B
B
V
D
D
G
L
L
C /
L
N
_
_
K
K
D
K
#
D
N
I P
D
O
N I
[ C
_
[ T
D
D
N I
N
U
T
: 9
: 9
T
T
N
] 0
] 0
T
A
M
E
T
P
P
P
P
O
O
O
Y
DD
W
W
W
W
I
I
I
U
U
U
N
N
-
N
P
T
T
T
R
R
R
R
E
of 2.5V, an AV
P
T "
"
T "
T "
F
T "
N
P
G
A
A
t a
y s
C
o
B
o
n
n
t o
o r
u r
u r
u r
u r
o
n
w
w
h t
_
a
a
c
m
u
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e
" e
r e
" e
N I
c
r e
o l
o l
e
h
n
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o
p
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g
g
T
d
s
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n
e l
s
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C
a
n
u
e
n
p
g
F
m
o
o l
e f
m
DD
e
p
e
z i
o
o r
2
e
w
c
e
p
k c
e r
d
w
e
e
t a
. n
e t
u
DD
, y l
t n
b
d
r e
is grounded, the PLL is turned off and bypassed for test
n
f
o i
n
a
b
e r
d
f o
r a
c
L
d
k c
2
a
n
V
e
of 2.5V and differential data input and output levels.
s
q
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5 .
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d
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u
u
i w
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p
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c
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c
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s
l a i
f o
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p
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p
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h
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