ICS95V157AGLFT IDT, Integrated Device Technology Inc, ICS95V157AGLFT Datasheet - Page 5

• Manufacturer Part Number: ICS95V157AGLFT
• Description: IC CLK DVR SSTL_2 2.5V 48-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of ICS95V157AGLFT

• Input: Clock
• Output: SSTL-2
• Frequency - Max: 233MHz
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Frequency-max: 233MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 95V157AGLFT

Notes:
1.
2.
3.
4. Static phase offset shifted by design.
0501C—11/24/08
T
Max clock frequency
Application Frequency
Range
Input clock duty cycle
CLK stabilization
Low-to high level
propagation delay time
High-to low level propagation
delay time
Output enable time
Output disable time
Period jitter
Half-period jitter
Input clock slew rate
Output clock slew rate
Cycle to Cycle Jitter
Phase error
Output to Output Skew
Timing Requirements
Switching Characteristics (see note 3)
A
= 0 - 85°C; Supply Voltage A
Refers to transition on noninverting output in PLL bypass mode.
While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=t
the cycle (t
Switching characteristics guaranteed for application frequency range.
PARAMETER
PARAMETER
c
) decreases as the frequency goes up.
1
VDD
SYMBOL
t
freq
SYMBOL
t(jit_hper)
(phase error)
T
freq
T
, V
T
d
STAB
cyc
T
t
t
t
tin
tdis
jit (per)
PLH
t
PLL
t
sl(o)
DD
App
skew
sl(i)
EN
op
-T
1
1
= 2.5 V +/- 0.2V (unless otherwise stated)
cyc
4
2.5V+0.2V @ 25
2.5V+0.2V @ 25
CLK_IN to any output
CLK_IN to any output
PD# to any output
PD# to any output
100MHz to 200MHz
100MHz to 200MHz
100MHz to 200MHz
CONDITIONS
CONDITION
5
o
o
C
C
wH
MIN
45
95
40
/t
c
, where
MIN
-30
-75
-50
1
1
MAX
233
210
60
15
TYP
5.5
5.5
UNITS
5
5
0
MHz
MHz
ICS95V157
µs
%
MAX
2.5
30
30
60
50
60
4
UNITS
V/ns
V/ns
ns
ns
ns
ns
ps
ps
ps
ps
ps