ICS97ULP844AHLFT IDT, Integrated Device Technology Inc, ICS97ULP844AHLFT Datasheet

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ICS97ULP844AHLFT

Manufacturer Part Number
ICS97ULP844AHLFT
Description
IC CLOCK DRIVER 1.8V LP 28-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Driverr
Datasheet

Specifications of ICS97ULP844AHLFT

Input
Clock
Output
Clock
Frequency - Max
370MHz
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
28-BGA
Frequency-max
370MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
97ULP844AHLFT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS97ULP844AHLFT
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Recommended Application:
Product Description/Features:
Switching Characteristics:
Block Diagram
CLK_INC
1110B—06/06/05
CLK_INT
1.8V Low-Power Wide-Range Frequency Clock Driver
FB_INC
FB_INT
10K-100k
* The Logic Detect (LD) powers down the device when a
logic low is applied to both CLK_INT and CLK_INC.
DDR2 Memory Modules / Zero Delay Board Fan Out
Provides complete DDR DIMM logic solution with
ICSSSTU32864/SSTUF32864/SSTUF32866
Low skew, low jitter PLL clock driver
1 to 4 differential clock distribution (SSTL_18)
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
Auto PD when input signal is at a certain logic state
Period jitter: 40ps
Half-period jitter: 60ps
CYCLE - CYCLE jitter 40ps
OUTPUT - OUTPUT skew: 40ps
AV
OE
OS
DD
GND
Integrated
Circuit
Systems, Inc.
Powerdown
Control and
Test Logic
PLL
LD*
PLL bypass
LD* or OE
FB_OUTT
FB_OUTC
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
A
B
C
D
Ball Assignments
E
F
A
B
C
D
E
F
Pin Configuration
1
CK_INC
CK_INT
CLKT0
CLKC3
AGND
AVDD
1
28-Ball BGA
2
Top View
CLKC0
CLKT3
GND
GND
ICS97ULP844A
V
OE
3
2
DD
4
CLKC1
CLKC2
V
V
NB
NB
3
DD
DD
5
CLKT1
CLKT2
GND
GND
V
OS
4
DD
FB_OUTC
FB_OUTT
FB_INT
FB_INC
GND
GND
5

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ICS97ULP844AHLFT Summary of contents

Page 1

Integrated Circuit Systems, Inc. 1.8V Low-Power Wide-Range Frequency Clock Driver Recommended Application: • DDR2 Memory Modules / Zero Delay Board Fan Out • Provides complete DDR DIMM logic solution with ICSSSTU32864/SSTUF32864/SSTUF32866 Product Description/Features: • Low skew, low jitter PLL clock ...

Page 2

ICS97ULP844A Pin Descriptions ...

Page 3

Function Table ...

Page 4

ICS97ULP844A Absolute Maximum Ratings Supply Voltage (VDDQ & AVDD -0.5V to 2.5V Logic Inputs . . . . . . . . . . . . . . . . . ...

Page 5

Recommended Operating Condition (see note1 70°C; Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) A PARAMETER SYMBOL Supply Voltage V DDQ Low level input voltage V High level input voltage V DC ...

Page 6

ICS97ULP844A Timing Requirements 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) A PARAMETER SYMBOL Max clock frequency Application Frequency Range Input clock duty cycle CLK stabilization 1 Switching Characteristics T = ...

Page 7

VDD/2 ICS97ULP844A -VDD FB_OUTC FB_OUTT X 1110B—06/06/05 Parameter Measurement Information (CLKC) ICS97ULP844 GND Figure 1. IBIS Model Output Load GND R = 10Ω 0Ω ...

Page 8

ICS97ULP844A CLK_INC CLK_INT FB_INC FB_INT FB_OUTC FB_OUTT FB_OUTC FB_OUTT FB_OUTC FB_OUTT X 1110B—06/06/05 Parameter Measurement Information t ( ...

Page 9

Y , FB_OUTC FB_OUTT X 20% Clock Inputs and Outputs 1110B—06/06/05 Parameter Measurement Information t jit(hper_n) t jit(hper_n+ jit(hper) jit(hper_n) 2xf O Figure 7. Half-Period Jitter 80% t slr ...

Page 10

ICS97ULP844A CK CK FBIN FBIN SSC OFF t ( )dyn Figure 10. Time delay between OE and Clock Output (Y, Y) 1110B—06/06/ SSC )dyn Figure 9. Dynamic Phase ...

Page 11

Place the 2200pF capacitor close to the PLL. - Use a wide trace for the PLL analog power & ground. Connect PLL & caps to AGND trace & connect trace to one GND via (farthest from PLL). - Recommended ...

Page 12

ICS97ULP844A SYMBOL Ordering Information ICS97ULP844AH(LF)-T Example: ICS XXXX y H (LF)- T 1110B—06/06/05 Millimeter MIN NOM MAX 0.80 0.90 1.00 0.165 0.20 0.235 0.16 0.20 0.24 0.475 0.50 0.525 0.35 ...

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