ICS9DB106BGLF IDT, Integrated Device Technology Inc, ICS9DB106BGLF Datasheet - Page 10

• Manufacturer Part Number: ICS9DB106BGLF
• Description: IC BUFFER 6OUTPUT PCI 28-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Zero Delay Bufferr
• Series: -r

Specifications of ICS9DB106BGLF

• Input: Clock
• Output: HCSL
• Frequency - Max: 101MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Frequency-max: 101MHz
• Number Of Elements: 1
• Supply Current: 150mA
• Pll Input Freq (min): 80MHz
• Pll Input Freq (max): 105MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSSOP
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Compliant
• Other names: 9DB106BGLF

IDT
SMBusTable: Device Control Register, READ/WRITE ADDRESS (D4/D5)
SMBusTable: Output Enable Register
SMBusTable: Function Select Register
SMBusTable: Vendor & Revision ID Register
9DB106
Six Output Differential Buffer for PCIe Gen 2
®
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Six Output Differential Buffer for PCIe Gen 2
Byte 0
Byte 1
Byte 2
Byte 3
24,23
18,17
11,12
5,6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pin #
Pin #
Pin #
Pin #
PLL BW #adjust
PLL Enable
SW_EN
PCIEX5
PCIEX3
PCIEX2
PCIEX0
Name
Name
Name
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Control Function Type
Bypasses PLL for
Control Function Type
Control Function Type
Control Function Type
Enables SMBus
Output Control
Output Control
Output Control
Output Control
REVISION ID
VENDOR ID
Selects PLL
Bandwidth
board test
Control
10
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
R
R
PLL controlled
(fan out mode)
PLL bypassed
by SMBus
registers
Low BW
Disable
Disable
Disable
Disable
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
by device pins
PLL controlled
PLL enabled
(ZDB mode)
High BW
Enable
Enable
Enable
Enable
1
1
1
1
-
-
-
-
-
-
-
-
9DB106
PWD
PWD
PWD
PWD
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
0
0
0
1
0
0
0
1
REV J 01/27/11