ICS9DB106BGLF IDT, Integrated Device Technology Inc, ICS9DB106BGLF Datasheet - Page 4

• Manufacturer Part Number: ICS9DB106BGLF
• Description: IC BUFFER 6OUTPUT PCI 28-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Zero Delay Bufferr
• Series: -r

Specifications of ICS9DB106BGLF

• Input: Clock
• Output: HCSL
• Frequency - Max: 101MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Frequency-max: 101MHz
• Number Of Elements: 1
• Supply Current: 150mA
• Pll Input Freq (min): 80MHz
• Pll Input Freq (max): 105MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSSOP
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Compliant
• Other names: 9DB106BGLF

IDT
1
2
TA = T
Operating Supply Current
1
2
Electrical Characteristics - Absolute Maximum Ratings
Electrical Characteristics - Input/Supply/Common Output Parameters
Low-level Output Voltage
Guaranteed by design and characterization, not 100% tested in production.
Guaranteed by design and characterization, not 100% tested in production.
Except differential input clock
Input Spread Spectrum
Operation under these conditions is neither implied nor guaranteed.
Modulation Frequency
Clock/Data Rise Time
9DB106
Six Output Differential Buffer for PCIe Gen 2
Clock/Data Fall Time
®
3.3V Logic Supply Voltage
3.3V Core Supply Voltage
Ambient Operating
Input High Voltage
Input High Current
Input Capacitance
Input Low Voltage
Input Low Current
Current sinking at
Six Output Differential Buffer for PCIe Gen 2
Input Frequency
Clk Stabilization
Pin Inductance
SMBus Voltage
Junction Temperature
Storage Temperature
Input ESD protection
PARAMETER
SCLK/SDATA
SCLK/SDATA
Temperature
Input High Voltage
Input High Voltage
V
Input Low Voltage
COM
OL
PARAMETER
= 0.4 V
or T
IND;
Supply Voltage VDD = 3.3 V +/-5%
SYMBOL
I
I
DD3.3OP
T
PULLUP
T
C
T
T
T
V
V
V
L
C
V
I
I
STAB
I
COM
F
RI2C
FI2C
IL1
IL2
OUT
IND
IH
pin
DD
OL
IH
IN
IL
SYMBOL
i
ESD prot
VDDA
V
VDD
V
IHSMB
V
Ts
Tj
IH
IL
V
From VDD reaching 3.1V and
V
all differential pairs tri-stated
IN
Full Active, C
IN
Output pin capacitance
Except for SMBus interface
SMBus clock and data pins
= 0 V; Inputs with no pull-
= 0 V; Inputs with pull-up
Triangular Modulation
Commmercial range
(Min VIH + 0.15) to
(Max VIL - 0.15) to
input clock stable
(Min VIH + 0.15)
(Max VIL - 0.15)
Industrial range
Human Body Model
CONDITIONS
Logic Inputs
3.3 V +/-5%
3.3 V +/-5%
up resistors
V
V
CONDITIONS
@ I
resistors
DD
IN
= 3.3 V
= V
PULLUP
L
= Full load;
DD
4
GND-0.5
V
2000
SS
MIN
MIN
-200
-65
-40
2.7
80
30
-5
-5
0
2
4
- 0.3
TYP
TYP
100
130
30
V
V
DD
MAX
5.5V
150
125
DD
4.6
4.6
+0.5V
MAX
1000
150
105
300
9DB106
0.8
4.5
1.8
5.5
0.4
70
85
40
33
5
7
5
+ 0.3
UNITS
UNITS Notes
MHz
kHz
°
°C
mA
mA
mA
V
V
V
V
V
V
ms
C
uA
uA
uA
nH
pF
pF
°C
°C
ns
ns
REV J 01/27/11
V
V
V
V
NOTES
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1