ICS932S401EGLF IDT, Integrated Device Technology Inc, ICS932S401EGLF Datasheet - Page 19

IC TIMING CTRL HUB PROGR 56TSSOP

ICS932S401EGLF

Manufacturer Part Number
ICS932S401EGLF
Description
IC TIMING CTRL HUB PROGR 56TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Timing Control Hubr
Datasheet

Specifications of ICS932S401EGLF

Input
Crystal
Output
Clock
Frequency - Max
400MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-TSSOP
Frequency-max
400MHz
Number Of Elements
3
Supply Current
350mA
Pll Input Freq (min)
14.31818MHz
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
0C to 70C
Package Type
TSSOP
Output Frequency Range
33.33 to 400MHz
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.465V
Operating Temperature Classification
Commercial
Pin Count
56
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
932S401EGLF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS932S401EGLFT
Manufacturer:
IDT
Quantity:
6 363
Part Number:
ICS932S401EGLFT
Manufacturer:
ICS
Quantity:
20 000
PD Assertion
PD# should be sampled high by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be
held low on their next high to low transition.
All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register
determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven.
When the drive mode corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at 2 x
Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be tristated.
See SMBus Byte 4 for additional information.
Notes:
1. Refer to SMBus Byte 4 for additional information.
0921G—08/24/09
PD, Power Down
PD is an asynchronous active high input used to shut off all clocks cleanly prior to system power down.
When PD is asserted, all clocks will be driven low before turning off the VCO. All clocks will start without glitches when PD is
de-asserted.
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SRC#, 100MHz
REF, 14.31818
CPU, 133MHz
SRC, 100MHz
USB, 48MHz
PCI, 33MHz
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