ICS9EPRS475CGLFT IDT, Integrated Device Technology Inc, ICS9EPRS475CGLFT Datasheet - Page 16

• Manufacturer Part Number: ICS9EPRS475CGLFT
• Description: IC EMBEDDED PC MAIN CLK 56TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS9EPRS475CGLFT

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT
5
CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK
meets CLK#.
6
7
8
10
11
Notes on Electrical Characteristics:
Guaranteed by design and characterization, not 100% tested in production.
Single-ended measurement at crossing point. Value is maximum – minimum over all time. DC value of common mode is
not important due to the blocking cap.
Minimum Frequency is a result of 0.5% down spread spectrum
Differential measurement through the range of ±100 mV, differential signal must remain monotonic and within slew rate
spec when crossing through this region.
9
0V VD. VD(max) is the largest amplitude allowed.
AC Electrical Characteristics - Low-Power DIF Outputs: CPUKG and HTT
CPU, DIF HTT Jitter - Cycle to
Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of
Max difference of t
Accumulated tjc.over a 10 µs time period, measured with JIT2 TIE at 50ps interval.
VD(PK-PK) is the overall magnitude of the differential signal.
VD(min) is the amplitude of the ring-back differential measurement, guaranteed by design, that ring-back will not cross
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
The difference in magnitude of two adjacent VD_DC measurements. VD_DC is the stable post overshoot and ring-back part of the signal.
9EPRS475
System Clock for Embedded AMD
®
Peak to Peak Differential
Crossing Point Variation
Falling Edge Slew Rate
Rising Edge Slew Rate
System Clock for Embedded AMD
Long Term Accuracy
Slew Rate Variation
Amplitude Variation
Accumulated Jitter
Differential Voltage
CPU[1:0] Skew
PARAMETER
Frequency
Duty Cycle
Voltage
Cycle
CYCLE
between any two adjacent cycles.
CPU
SYMBOL
CPUJ
ΔV
V
t
S
S
D(PK-PK)
D
ΔV
ppm
SLVAR
t
JACC
TM
V
CROSS
RISE
FALL
CYC
SKEW10
f
D
based Systems
D
C2C
TM
based Systems
Change in V
Single-ended Measurement
Single-ended Measurement
Differential Measurement
Differential Measurement
Differential Measurement
Differential Measurement
Differential Measurement
Differential Measurement
Differential Measurement
Spread Specturm On
Spread Specturm Off
CONDITIONS
See Notes
D
DC cycle to cycle
16
198.8
-300
MIN
400
200
-75
0.5
0.5
45
TYP
+300
2400
1200
MAX
140
200
150
100
10
10
20
55
75
1
UNITS NOTES
MHz
V/ns
V/ns
ppm
mV
mV
mV
mV
ps
ns
ps
%
%
1,2,5
1,11
1,10
1,3
1,4
1,4
1,6
1,7
1,8
1,9
1
1
1
1615B—04/26/10