ICS953002CFLF IDT, Integrated Device Technology Inc, ICS953002CFLF Datasheet - Page 22

• Manufacturer Part Number: ICS953002CFLF
• Description: IC TIMING CTRL HUB P4 56-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Timing Control Hubr

Specifications of ICS953002CFLF

• Input: Clock
• Output: Clock
• Frequency - Max: 66MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Frequency-max: 66MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 953002CFLF

0924—11/18/09
I
I
B1b[4:3] = 00 is invalid
I
I
2
2
2
2
C Table: Device Control Register
C Table: Device Control Register
C Table: Output Control Register
C Table: Output Control Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 0
Byte 1
Byte 2
Byte 3
Integrated
Circuit
Systems, Inc.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pin #
Pin #
Pin #
Pin #
SEL24_48MHz
M/N Enable bit
24_48MHz
FS Source
Reserved
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
CPUFS4
CPUFS3
CPUFS2
CPUFS1
CPUFS0
SS_EN1
SS_EN2
3V66_2
3V66_1
3V66_0
ITP_EN
48MHz
Mode 0
Name
Name
Name
Name
REF0
REF1
ROD
FSL2
FSL1
FSL0
FS4
FS3
PLL1 Spread Enable
PLL2 Spread Enable
Frequency H/W IIC
Control Function
Reset On Demand
Control Function
Control Function
Control Function
M/N Programming
Freq/Div Sel Bit 4
Freq/Div Sel Bit 3
Freq/Div Sel Bit 2
Freq/Div Sel Bit 1
Freq/Div Sel Bit 0
PLL1 VCO Sel b4
PLL1 VCO Sel b3
PLL1 VCO Sel b2
PLL1 VCO Sel b1
PLL1 VCO Sel b0
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Select
Output Select
Output Select
Reserved
Enable bit
Select
22
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
See Table 1b: PLL2 AGP/PCI Frequency
PCIEXCLKT/C0
PCIEXCLKT/C5
Latch Inputs
See Table 1a: PLL1 Rom VCO
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
48MHz
Frequency Selection Table
OFF
OFF
0
0
0
0
-
Selection Table
CPU_STOP/PCI_P
CPUCLKT/C2
CIEX_STOP
24MHz
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
ON
ON
IIC
1
1
1
1
-
ICS953002
Latch
Latch
Latch
PWD
PWD
PWD
PWD
latch
latch
latch
latch
latch
0
1
0
1
1
0
X
X
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1