ICS953002CFLF IDT, Integrated Device Technology Inc, ICS953002CFLF Datasheet - Page 26

• Manufacturer Part Number: ICS953002CFLF
• Description: IC TIMING CTRL HUB P4 56-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Timing Control Hubr

Specifications of ICS953002CFLF

• Input: Clock
• Output: Clock
• Frequency - Max: 66MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Frequency-max: 66MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 953002CFLF

0924—11/18/09
I
I
I
I
2
2
2
2
C Table: Output Divider Control Register
C Table: PLL2 Frequency Control Register
C Table: PLL2 Frequency Control Register
C Table: PLL2 Spread Spectrum Control Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 16
Byte 17
Byte 18
Byte 19
Integrated
Circuit
Systems, Inc.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pin #
Pin #
Pin #
Pin #
AGP/PCIDiv3
AGP/PCIDiv2
AGP/PCIDiv1
AGP/PCIDiv0
Reserved
Reserved
Reserved
Reserved
N Div8
N Div9
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
Name
Name
Name
Name
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
N Divider Programming
AGP/PCI Divider Ratio
Programming b(7:0)
N Divider Prog bit 8
N Divider Prog bit 9
Control Function
Programmaing Bits
Control Function
Control Function
Control Function
Programming bits
Spread Spectrum
Reserved
Reserved
Reserved
Reserved
M Divider
b(7:0)
PLL1
26
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
VCO Frequency = 14.318 x [NDiv(9:0)+8]
VCO Frequency = 14.318 x [NDiv(9:0)+8]
and 20 will program the spread pecentage
Divier in Byte 17 and 18 will configure the
Divier in Byte 17 and 18 will configure the
0000:/4
0001:/3
0010:/5
0011:/9
PLL2 VCO frequency. Default at power
PLL2 VCO frequency. Default at power
The decimal representation of M and N
The decimal representation of M and N
These Spread Spectrum bits in Byte 19
up = latch-in or Byte 0 Rom table.
up = latch-in or Byte 0 Rom table.
0
0
0
0
-
-
-
-
0110:/10 1010:/20 1110:/40
0111:/18 1011:/36 1111:/72
0100:/8
0101:/6
/ [MDiv(5:0)+2]
/ [MDiv(5:0)+2]
of PLL2
1000:/16 1100:/32
1001:/12 1101:/24
1
1
1
1
-
-
-
-
ICS953002
PWD
PWD
PWD
PWD
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X