SI5368B-C-GQ Silicon Laboratories Inc, SI5368B-C-GQ Datasheet - Page 21

• Manufacturer Part Number: SI5368B-C-GQ
• Description: IC CLK MULTIPLIER ATTEN 100TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5368B-C-GQ

• Package / Case: 100-TQFP, 100-VQFP
• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Frequency-max: *
• Number Of Circuits: 1
• Maximum Input Frequency: 710 MHz
• Minimum Input Frequency: 0.002 MHz
• Output Frequency Range: 0.002 MHz to 808 MHz
• Supply Voltage (max): 2.75 V
• Supply Voltage (min): 1.71 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V, 2.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reset value = 0100 0010
Reset value = 0000 0101
Register 2.
Register 3.
Name
Name
Type
Type
Bit
Bit
7:4
3:0
7:6
Bit
Bit
5
BWSEL_REG
CKSEL_REG
Reserved
CKSEL_REG [1:0]
DHOLD
Name
Name
D7
D7
[3:0]
[1:0]
R/W
BWSEL_REG.
Selects nominal f3dB bandwidth for PLL. See the DSPLLsim for settings. After
BWSEL_REG is written with a new value, an ICAL is required for the change to take
effect.
Reserved.
CKSEL_REG.
If the device is operating in manual register-based clock selection mode
(AUTOSEL_REG = 00), and CKSEL_PIN = 0, then these bits select which input clock
will be the active input clock. If CKSEL_PIN = 1, the CKSEL[1:0] input pins continue to
control clock selection and CKSEL_REG is of no consequence.
00: CKIN_1 selected.
01: CKIN_2 selected.
10: CKIN_3 selected.
11: CKIN_4 selected.
DHOLD.
Forces the part into digital hold. This bit overrides all other manual and automatic clock
selection controls.
0: Normal operation.
1: Force digital hold mode. Overrides all other settings and ignores the quality of all of the
input clocks.
BWSEL_REG [3:0]
D6
D6
R/W
DHOLD
R/W
D5
D5
Preliminary Rev. 0.41
SQ_ICAL
R/W
D4
D4
Function
Function
D3
D3
D2
D2
Reserved
Reserved
R
R
D1
D1
Si5368
D0
D0
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