MC100EP196FAR2G ON Semiconductor, MC100EP196FAR2G Datasheet - Page 13
![IC PROGRAM DELAY 3.3V ECL 32LQFP](/photos/31/26/312678/296-32-tqfp_sml.jpg)
MC100EP196FAR2G
Manufacturer Part Number
MC100EP196FAR2G
Description
IC PROGRAM DELAY 3.3V ECL 32LQFP
Manufacturer
ON Semiconductor
Series
100EPr
Type
Programmable Delay Chipr
Datasheet
1.MC100EP196FAG.pdf
(18 pages)
Specifications of MC100EP196FAR2G
Input
ECL, LVCMOS, LVTTL
Output
ECL
Frequency - Max
1.2GHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-LQFP
Frequency-max
1.2GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
MC100EP196FAR2GOS
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC100EP196FAR2G
Manufacturer:
SANYO
Quantity:
8 000
Company:
Part Number:
MC100EP196FAR2G
Manufacturer:
ON Semiconductor
Quantity:
10 000
Cascading Multiple EP196s
internal cascade circuitry has been included. This circuitry
allows for the cascading of multiple EP196s without the
need for any external gating. Furthermore, this capability
requires only one more address line per added E196.
Obviously, cascading multiple programmable delay chips
will result in a larger programmable range; however, this
increase is at the expense of a longer minimum delay.
two EP196s. As can be seen, this scheme can easily be
INPUT
To increase the programmable range of the EP196,
Figure 6 illustrates the interconnect scheme for cascading
D8
D9
D10
IN
IN
V
V
V
BB
EF
CF
D7
Need if Chip #3 is used
D6
D5
CHIP #2
D4
EP196
V
EE
Figure 6. Cascading Interconnect Architecture
D3
D2
FTUNE
D1
V
V
V
V
D0
CC
CC
CC
EE
http://onsemi.com
Q
Q
13
expanded for larger EP196 chains. The D10 input of the
EP196 is the cascade control pin and when assert
HIGH switches output pin CASCADE to HIGH and
pin CASCADE to LOW. With the interconnect scheme of
Figure 6 when D10 is asserted, it signals the need for a larger
programmable range than is achievable with a single device.
The A11 address can be added to generate a cascade output
for the next EP196. For a 2−device configuration, A11 is not
required.
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
D8
D9
D10
IN
IN
V
V
V
BB
EF
CF
D7
D6
D5
ADDRESS BUS
D4
CHIP #1
EP196
V
EE
D3
D2 D1
FTUNE
V
V
V
V
D0
CC
CC
CC
EE
Q
Q
DAC
OUTPUT