MC100EP196FAR2G ON Semiconductor, MC100EP196FAR2G Datasheet - Page 3
![IC PROGRAM DELAY 3.3V ECL 32LQFP](/photos/31/26/312678/296-32-tqfp_sml.jpg)
MC100EP196FAR2G
Manufacturer Part Number
MC100EP196FAR2G
Description
IC PROGRAM DELAY 3.3V ECL 32LQFP
Manufacturer
ON Semiconductor
Series
100EPr
Type
Programmable Delay Chipr
Datasheet
1.MC100EP196FAG.pdf
(18 pages)
Specifications of MC100EP196FAR2G
Input
ECL, LVCMOS, LVTTL
Output
ECL
Frequency - Max
1.2GHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-LQFP
Frequency-max
1.2GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
MC100EP196FAR2GOS
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC100EP196FAR2G
Manufacturer:
SANYO
Quantity:
8 000
Company:
Part Number:
MC100EP196FAR2G
Manufacturer:
ON Semiconductor
Quantity:
10 000
Table 1. PIN DESCRIPTION
1. SETMIN will override SETMAX if both are high. SETMAX and SETMIN will override all D[0:10] inputs.
2. All V
23, 25, 26, 27,
29, 30, 31, 32,
13, 18, 19, 22
9, 28
1, 2
Pin
10
12
14
15
16
17
21
20
11
3
4
5
6
7
8
CC
and V
EE
CASCADE
CASCADE
SETMAX
SETMIN
FTUNE
pins must be externally connected to Power Supply to guarantee proper operation.
Name
D[0:9]
D[10]
LEN
V
V
V
V
V
EN
IN
IN
Q
Q
CC
BB
EF
CF
EE
LVCMOS, LVTTL,
LVCMOS, LVTTL,
Analog Input
ECL Output
ECL Output
ECL Output
ECL Output
ECL Input
ECL Input
ECL Input
ECL Input
ECL Input
ECL Input
ECL Input
ECL Input
I/O
−
−
−
−
−
Default State
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
http://onsemi.com
−
−
−
−
−
−
−
−
−
−
3
Single−ended Parallel Data Inputs [0:9]. Internal 75 kW to V
(Note 1)
Single−ended CASCADE/CASCADE Control Input. Internal 75 kW
to V
Noninverted Differential Input. Internal 75 kW to V
Inverted Differential Input. Internal 75 kW to V
ECL Reference Voltage Output
Reference Voltage for ECL Mode Connection
LVCMOS, ECL, OR LVTTL Input Mode Select
Negative Supply Voltage. All V
ted to Power Supply to Guarantee Proper Operation. (Note 2)
Positive Supply Voltage. All V
ted to Power Supply to Guarantee Proper Operation. (Note 2)
Single−ended D pins LOAD / HOLD input. Internal 75 kW to V
Single−ended Minimum Delay Set Logic Input. Internal 75 kW to
V
Single−ended Maximum Delay Set Logic Input. Internal 75 kW to
V
Inverted Differential Cascade Output for D[10] Input. Typically Ter-
minated with 50 W to V
Noninverted Differential Cascade Output for D[10] Input. Typically
Terminated with 50 W to V
Single−ended Output Enable Pin. Internal 75 kW to V
Fine Tuning Input.
Noninverted Differential Output. Typically Terminated with 50 W to
V
Inverted Differential Output. Typically Terminated with 50 W to
V
EE
EE
TT
TT
EE
. (Note 1)
. (Note 1)
= V
= V
. (Note 1)
CC
CC
− 2 V.
− 2 V.
TT
= V
TT
Description
= V
CC
CC
EE
CC
− 2 V.
Pins must be externally Connec-
Pins must be Externally Connec-
− 2 V.
EE
.
EE
.
EE
.
EE
EE
.
.