SI5013-D-GM Silicon Laboratories Inc, SI5013-D-GM Datasheet - Page 15

• Manufacturer Part Number: SI5013-D-GM
• Description: IC CLOCK/DATA RECOVERY 28MLP
• Manufacturer: Silicon Laboratories Inc
• Type: Clock and Data Recovery (CDR)r

Specifications of SI5013-D-GM

• Input: Differential
• Output: CML
• Frequency - Max: 675MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 675MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 336-1277

4.11.2. Jitter Transfer
The
specifications related to SONET/SDH jitter transfer.
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter as a function of jitter frequency.
These measurements are made with an input test signal
that is degraded with sinusoidal jitter whose magnitude
is defined by the mask in Figure 9.
4.11.3. Jitter Generation
The Si5013 exceeds all relevant specifications for jitter
generation proposed for SONET/SDH equipment. The
jitter generation specification defines the amount of jitter
that may be present on the recovered clock and data
outputs when a jitter free input signal is provided. The
Si5013 typically generates less than 3.0 mUI
when presented with jitter-free input data.
4.12. RESET/DSPLL Calibration
The Si5013 achieves optimal jitter performance by
automatically calibrating the loop gain parameters within
the DSPLL on powerup. Calibration may also be
initiated by a high-to-low transition on the RESET/CAL
pin. The RESET/CAL pin must be held high for at least
1 µs. When RESET/CAL is released (set to low) the
digital logic resets to a known initial condition,
recalibrates the DSPLL, and begins to lock to the
incoming data stream. For a valid reset to occur when
using Reference mode, a proper, external reference
clock frequency must be applied.
4.13. Clock Disable
The Si5013 provides a clock disable pin (CLK_DSBL)
that is used to disable the recovered clock output
(CLKOUT). When the CLK_DSBL pin is asserted, the
Transfer
Figure 9. Jitter Transfer Specification
Si5013
Jitter
0.1 dB
exceeds
Acceptable
Range
SONET
Data Rate
OC-12
OC-3
all
Frequency
Fc
relevant
130
500
Fc
(kHz)
20 dB/Decade
Slope
Bellcore/ITU
rms
of jitter
Rev. 1.6
positive and negative terminals of CLKOUT are tied to
VDD through 100 Ω on-chip resistors.
4.14. Data Squelch
The Si5013 provides a data squelching pin (DSQLCH)
that is used to set the recovered data output (DOUT) to
binary zero. When the DSQLCH pin is asserted, the
DOUT+ signal is held low and the DOUT– signal is held
high. This pin can be is used to squelch corrupt data
during LOS and LOL situations. Care must be taken
when ac coupling these outputs; a long string of zeros
or ones will not be held through ac coupling capacitors.
4.15. Device Grounding
The Si5013 uses the GND pad on the bottom of the 28-
pin micro leaded package (QFN) for device ground. This
pad should be connected directly to the analog supply
ground. See Figure 15 on page 19 and Figure 16 on
page 23 for the ground (GND) pad location.
4.16. Bias Generation Circuitry
The Si5013 makes use of an external resistor to set
internal bias currents. The external resistor allows
precise generation of bias currents which significantly
reduces
implementations that use an internal resistor. The bias
generation circuitry requires a 10 kΩ (1%) resistor
connected between REXT and GND.
4.17. Voltage Regulator
The Si5013 operates from a 3.3 V external supply
voltage. Internally the device operates from a 2.5 V
supply. The Si5013 regulates 2.5 V internally down from
the external 3.3 V supply.
In addition to supporting 3.3 V systems, the on-chip
linear regulator offers better power supply noise
rejection versus a direct 2.5 V supply.
4.18. Differential Input Circuitry
The Si5013 provides differential inputs for both the high-
speed data (DIN) and the reference clock (REFCLK)
inputs. An example termination for these inputs is
shown in Figures 10 and 11, respectively. In
applications where direct dc coupling is possible, the
0.1 µF capacitors may be omitted. (LOS operation is
only guaranteed when ac coupled.) The data input
limiting amplifier requires an input signal with a
differential peak-to-peak voltage as specified in Table 2
on page 7 to ensure a BER of at least 10
REFCLK
requirement is also specified in Table 2.
power
input
differential
consumption
peak-to-peak
versus
Si5013
traditional
–12
voltage
. The
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