SI5013-D-GM Silicon Laboratories Inc, SI5013-D-GM Datasheet - Page 24

• Manufacturer Part Number: SI5013-D-GM
• Description: IC CLOCK/DATA RECOVERY 28MLP
• Manufacturer: Silicon Laboratories Inc
• Type: Clock and Data Recovery (CDR)r

Specifications of SI5013-D-GM

• Input: Differential
• Output: CML
• Frequency - Max: 675MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 675MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 336-1277

Si5013
D
Revision 0.2 to Revision 1.0
Revision 1.0 to Revision 1.1
Revision 1.1 to Revision 1.2
24
OCUMENT
Added Figure 4, “PLL Acquisition Time,” on page 6.
Table 2 on page 7
Table 3 on page 8
Table 4 on page 9
Removed “Hysteresis Dependency” Figure.
Added Figure 7, “LOS Signal Hysteresis,” on page
13.
Corrected error: Table 8 on page 19—changed
description for LOS_LVL from “LOS is disabled when
the voltage applied is less than 500 mV” to “LOS is
disabled when the voltage applied is less than
1.0 V.”
Corrected “Revision 0.2 to Revision 1.0” Change
List.
Table 4 on page 9
Added Figure 5, “LOS Response,” on page 6.
Updated Table 2 on page 7.
updated values.
updated values.
Updated Table 3 on page 8.
(REFCLK)
applied)
(reference-less operation)
goes out of Lock
goes into Lock
Updated values: Supply Current
Updated values: Power Dissipation
Updated values: Common Mode Input Voltage
Updated values: Output Common Mode Voltage
Updated values: Output Clock Rise Time
Updated values: Output Clock Fall Time
Updated values: Clock to Data Delay t
Updated values: Jitter Tolerance (OC-12)
Updated values: RMS Jitter Generation
Updated values: Peak-to-Peak Jitter Generation
Updated values: Acquisition Time (reference clock
Updated values: Acquisition Time
Updated values: Freq Difference at which Receive PLL
Updated values: Freq Difference at which Receive PLL
Updated values: Jitter Tolerance (OC-3)
Added “Output Common Mode Voltage (DOUT)” with
Added “Output Common Mode Voltage (CLKOUT)” with
Added “Output Clock Duty Cycle—OC-12/3.”
Added “Loss-of-Signal Response Time” with updated
C
HANGE
L
IST
Cf-D
Rev. 1.6
Revision 1.2 to Revision 1.3
Revision 1.3 to Revision 1.4
Revision 1.4 to Revision 1.5
values.
Updated Table 8 on page 19.
Updated Figure 16, “28-Lead Quad Flat No-Lead
(QFN),” on page 23.
Updated Table 9, “Package Diagram Dimensions,”
on page 23.
Updated Figure 16, “28-Lead Quad Flat No-Lead
(QFN),” on page 23.
Updated Table 9, “Package Diagram Dimensions,”
on page 23.
Updated " Features" on page 1.
Table 2 on page 7.
Table 3 on page 8.
Table 4 on page 9.
"3. Typical Application Schematic" on page 11.
"4.11. PLL Performance" on page 14.
Table 8 on page 19.
Updated "6. Ordering Guide" on page 22.
Updated Table 2 on page 7.
Updated Table 3 on page 8.
Updated "4.8. Loss-of-Signal (LOS)" on page 13.
Changed “clock input” to “DIN inputs” for Loss Of Signal
Changed dimension A.
Changed dimension E2.
Updated supply current values.
Updated power dissipation values.
Updated differential output voltage swing
(DOUT and CLKOUT).
Added output clock rate values.
Updated duty cycle values.
Updated slice accuracy values.
Updated jitter tolerance values (OC-12 mode).
Updated acquisition time values.
Updated reference clocks range.
Updated reference clocks tolerance.
Added 1% to Rext.
Removed OC-24 note.
Added no-hysteresis text to BER_LVL.
Added “X” to part number.
Added limits for V
Updated V
Updated T
Updated T
Revised SLICE specification.
OD
Cr-D
Cf-D
.
.
.
ICM
.