IDT5T93GL02PGGI IDT, Integrated Device Technology Inc, IDT5T93GL02PGGI Datasheet - Page 6

• Manufacturer Part Number: IDT5T93GL02PGGI
• Description: IC CLK BUFF/DVR MUX 1:2 20TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: TERABUFFER™ IIr
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of IDT5T93GL02PGGI

• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: Yes/Yes
• Input: CML, eHSTL, HSTL, LVDS, LVEPECL, LVPECL, LVTTL
• Output: LVDS
• Frequency - Max: 450MHz
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 450MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 5T93GL02PGGI; 800-1986-5; IDT5T93GL02PGGI

IDT5T93GL02 Data Sheet
Table 4D. LVDS DC Characteristics
NOTE 1: See Recommended Operating Range table.
NOTE 2: Typical values are at V
AC Electrical Characteristics
Table 5A. HSTL Differential Input AC Characteristics, T
NOTE 1.The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)
environment. This device meets the V
NOTE 2.A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment.
This device meets the V
NOTE 3.In all cases, input waveform timing is marked at the differential cross-point of the input signals.
NOTE 4.The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
IDT5T93GL02 REVISION B AUGUST 27, 2009
Symbol
V
V
∆V
V
∆V
I
I
Symbol
V
V
D
V
t
OS
OSD
R
OT(+)
OT(–)
OS
DIF
X
THI
H
/ t
OT
OS
F
Parameter
Differential Output Voltage for the
True Binary State
Differential Output Voltage for the
False Binary State
Change in V
Output States
Output Common Mode Voltage
(Offset Voltage)
Change in V
Output States
Outputs Short Circuit Current
Differential Outputs Short Circuit Current
Parameter
Input Signal Swing
Differential Input Signal Crossing Point
Duty Cycle
Input Timing Measurement Reference Level
Input Signal Edge Rate
X
OT
OS
specification under actual use conditions.
Between Complementary
Between Complementary
DD
(1)
= 2.5V, +25°C ambient.
(4)
DIF
(1)
(AC) specification under actual use conditions.
, T
A
= -40°C to 85°C
(2)
(3)
V
OUT+ and
Test Conditions
V
A
OUT+
= -40°C to 85°C
6
V
= V
OUT–
OUT–
= 0V
2.5V LVDS 1:2 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
Minimum
1.125
247
247
Typical
©2009 Integrated Device Technology, Inc.
1.2
12
6
Crossing Point
(2)
Value
750
50
1
2
Maximum
1.375
454
454
50
50
24
12
Units
V/ns
Units
mV
%
mV
mV
mV
mV
mA
mA
V
V
V