ICS854S204BGILF IDT, Integrated Device Technology Inc, ICS854S204BGILF Datasheet

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ICS854S204BGILF

Manufacturer Part Number
ICS854S204BGILF
Description
IC CLK FANOUT BUFFER 1:2 16TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Fanout Buffer (Distribution)r
Datasheet

Specifications of ICS854S204BGILF

Number Of Circuits
2
Ratio - Input:output
1:2
Differential - Input:output
Yes/Yes
Input
CML, LVDS, LVPECL, SSTL
Output
LVDS, LVPECL
Frequency - Max
3GHz
Voltage - Supply
2.375 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Frequency-max
3GHz
Number Of Outputs
8
Operating Supply Voltage (max)
3.465V
Operating Temp Range
-40C to 85C
Propagation Delay Time
0.5ns
Operating Supply Voltage (min)
2.375V
Mounting
Surface Mount
Pin Count
16
Operating Supply Voltage (typ)
2.5/3.3V
Package Type
TSSOP
Duty Cycle
51%
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
800-1964-5
854S204BGILF
ICS854S204BGILF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS854S204BGILF
Manufacturer:
IDT Integrated Device Technolo
Quantity:
135
Part Number:
ICS854S204BGILF
Manufacturer:
IDT
Quantity:
4 990
B
LOW SKEW, DUAL, PROGRAMMABLE 1-TO-2 DIFFERENTIAL-
TO-LVDS, LVPECL FANOUT BUFFER
G
accept most standard differential input levels. With the selection of
SEL_OUT signal, outputs can be selected be to either LVDS or
LVPECL levels. The ICS854S204I is characterized to operate
from either a 2.5V or a 3.3V power supply. Guaranteed out-
put and bank skew characteristics make the ICS854S204I
P
SEL_OUT F
IDT
ideal for those clock distribution applications demanding well
defined performance and repeatability.
HiPerClockS™
IC S
OWER
3
2
LOCK
ENERAL
3 .
5 .
SEL_OUT
/ ICS
S
V
V
nPCLKA
nPCLKB
E
PCLKA
PCLKB
S
O
O
L
UPPLY
p
p
_
0
1
V
O
r e
r e
LVDS, LVPECL FANOUT BUFFER
TAP
D
U
The ICS854S204I is a low skew, high performance
dual, programmable 1-to-2 Differential-to-LVDS,
LVPECL Fanout Buffer and a member of the
HiPerClock S™ family of High Performance Clock
Solutions from IDT. The PCLKx, nPCLKx pairs can
t a
t a
UNCTION
Pulldown
Pulldown
Pullup
Pulldown
Pullup
T
o i
o i
IAGRAM
C
D
n
n
ONFIGURATION
ESCRIPTION
T
O
ABLE
V
V
V
u
V
T
L
D
D
p t
A
V
D
T
D
L
P
A
V
P
t u
P
=
=
=
D
E
=
3
2
T
2
L
S
C
3 .
n
5 .
5 .
ABLE
e
L
c
V
V
v
V
l e
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
1
F
Two programmable differential LVDS or LVPECL output banks
Two differential clock input pairs
PCLKx, nPCLKx pairs can accept the following differential
input levels: LVDS, LVPECL, SSTL, CML
Maximum output frequency: 3GHz
Translates any single ended input signal to LVDS levels
with resistor bias on nPCLKx inputs
Output skew: 15ps (maximum)
Bank skew: 15ps (maximum)
Propagation delay: 500ps (maximum)
Additive phase jitter, RMS: 0.15ps (typical)
Full 3.3V or 2.5V power supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
EATURES
P
4.4mm x 5.0mm x 0.925mm package body
IN
A
nPCLKA
SSIGNMENT
PCLKA
nQA0
nQA1
GND
QA0
QA1
V
ICS854S204I
TAP
16-Lead TSSOP
G Package
Top View
1
2
3
4
5
6
7
8
ICS854S204BGI REV. A JUNE 4, 2008
16
15
14
13
12
11
10
9
nPCLKB
PCLKB
QB0
nQB0
QB1
nQB1
V
SEL_OUT
DD
ICS854S204I

Related parts for ICS854S204BGILF

ICS854S204BGILF Summary of contents

Page 1

LOW SKEW, DUAL, PROGRAMMABLE 1-TO-2 DIFFERENTIAL- TO-LVDS, LVPECL FANOUT BUFFER G D ENERAL ESCRIPTION The ICS854S204I is a low skew, high performance IC S dual, programmable 1-to-2 Differential-to-LVDS, HiPerClockS™ LVPECL Fanout Buffer and a member of the HiPerClock S™ family ...

Page 2

ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER ABLE IN ESCRIPTIONS ...

Page 3

ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER BSOLUTE AXIMUM ATINGS Supply Voltage Inputs, V -0. Outputs, I (LVPECL) O Continuous Current 50mA Surge Current 100mA Outputs, I (LVDS) O Continuous ...

Page 4

ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER T 4E. LVCMOS / LVTTL DC C ABLE HARACTERISTICS ...

Page 5

ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER T 4I. LVPECL DC C ABLE HARACTERISTICS ...

Page 6

ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER T 5C. LVPECL AC C ABLE HARACTERISTICS ...

Page 7

ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed ...

Page 8

ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER P ARAMETER V DD 3.3V±5% POWER SUPPLY LVDS + Float GND – 3.3V LVDS UTPUT OAD EST LVPECL V EE -1.3V±0.165V 3.3V LVPECL ...

Page 9

ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER P ARAMETER nQx Qx nQy Qy tsk( UTPUT KEW nQAx, nQBx QAx, QBx PERIOD t PW odc = x 100% t PERIOD ...

Page 10

ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER IRING THE IFFERENTIAL NPUT TO Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ V generated by ...

Page 11

ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER LVPECL LOCK NPUT NTERFACE The PCLK /nPCLK accepts LVPECL, LVDS, CML, SSTL and other differential signals. Both V and V SWING input requirements. Figures show ...

Page 12

ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER 3.3V, 2.5V LVDS D T RIVER ERMINATION A general LVDS interface is shown in Figure 100 differential transmission line environment, LVDS drivers require a matched load termination of ...

Page 13

ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER T 2.5V LVPECL O ERMINATION FOR Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating – 2V. For ...

Page 14

ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER P OWER This section provides information on power dissipation and junction temperature for the ICS854S204I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ...

Page 15

ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. F IGURE ...

Page 16

ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER P OWER This section provides information on power dissipation and junction temperature for the ICS854S204I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ...

Page 17

ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER ABLE VS IR LOW ABLE FOR JA Multi-Layer PCB, JEDEC Standard Test Boards T C RANSISTOR OUNT The transistor count for ICS854S204I is: 454 P ...

Page 18

ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER ABLE RDERING NFORMATION ...

Page 19

ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT © 2008 Integrated Device Technology, Inc. All rights reserved. Product ...

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