ICS558G-02 IDT, Integrated Device Technology Inc, ICS558G-02 Datasheet

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ICS558G-02

Manufacturer Part Number
ICS558G-02
Description
IC CLK DVR PECL/CMOS 16-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
ClockBlocks™r
Type
Fanout Buffer (Distribution), Dividerr
Datasheet

Specifications of ICS558G-02

Number Of Circuits
1
Ratio - Input:output
1:4
Differential - Input:output
Yes/No
Input
LVHSTL
Output
CMOS
Frequency - Max
250MHz
Voltage - Supply
3.15 V ~ 3.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Number Of Outputs
4
Operating Supply Voltage (max)
3.5V
Operating Temp Range
0C to 70C
Propagation Delay Time
12ns
Operating Supply Voltage (min)
3.15V
Mounting
Surface Mount
Pin Count
16
Operating Supply Voltage (typ)
3.3V
Package Type
TSSOP
Input Frequency
250MHz
Duty Cycle
55%
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Frequency-max
-
Lead Free Status / Rohs Status
Not Compliant
Other names
558G-02
LVHSTL TO CMOS CLOCK DIVIDER
Description
The ICS558-02 accepts a high-speed LVHSTL input and
provides four CMOS low skew outputs from a selectable
internal divider (divide by 3, divide by 4). The four outputs
are split into two banks of two outputs. Each bank has a
separate output enable to tri-state the output buffers.
The ICS558-02 is a member of the ICS Clock Blocks
family of clock generation, synchronization, and distribution
devices.
Block Diagram
IDT™ / ICS™ LVHSTL TO CMOS CLOCK DIVIDER
HCLK
HCLK
SEL
TM
Output Divide
/3 or /4
GND
VDD
4
3
1
Features
16-pin TSSOP package
LVHSTL inputs
Accepts up to 250 MHz input frequency
Four low skew (<250 ps) outputs
Selectable internal divider of 3 or 4
Operating voltage of 3.3 V
OE0
OE1
CLK1
CLK2
CLK3
CLK4
ICS558-02
DATASHEET
ICS558-02
REV D 020504

Related parts for ICS558G-02

ICS558G-02 Summary of contents

Page 1

LVHSTL TO CMOS CLOCK DIVIDER Description The ICS558-02 accepts a high-speed LVHSTL input and provides four CMOS low skew outputs from a selectable internal divider (divide by 3, divide by 4). The four outputs are split into two banks of ...

Page 2

ICS558-02 LVHSTL TO CMOS CLOCK DIVIDER Pin Assignment SEL 1 VDD 2 VDD 3 HCLK 4 HCLK 5 GND 6 GND 7 OE0 8 16 Pin 173 Mil (0.65mm) TSSOP Pin Descriptions Pin Pin Number Name 1 SEL 2 VDD ...

Page 3

ICS558-02 LVHSTL TO CMOS CLOCK DIVIDER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS558-02. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of ...

Page 4

ICS558-02 LVHSTL TO CMOS CLOCK DIVIDER AC Electrical Characteristics VDD = 3.3 V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise stated. Parameter Input Frequency Output Rise Time Output Fall Time Skew (between any two output clocks) Propagation ...

Page 5

... ICS558G-02 558G-02T ICS558G-02 While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied ...

Page 6

ICS558-02 LVHSTL TO CMOS CLOCK DIVIDER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 ...

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