ICS558G-01LF IDT, Integrated Device Technology Inc, ICS558G-01LF Datasheet

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ICS558G-01LF

Manufacturer Part Number
ICS558G-01LF
Description
IC CLK DVR PECL/CMOS 16-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Fanout Buffer (Distribution), Divider, Multiplexerr
Series
ClockBlocks™r
Datasheet

Specifications of ICS558G-01LF

Number Of Circuits
1
Ratio - Input:output
1:4
Differential - Input:output
Yes/No
Input
CMOS, PECL
Output
3-State, CMOS
Frequency - Max
250MHz
Voltage - Supply
2.375 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Frequency-max
250MHz
Number Of Clock Inputs
2
Output Logic Level
CMOS
Operating Supply Voltage (min)
3V
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Package Type
TSSOP
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Signal Type
CMOS/PECL
Mounting
Surface Mount
Pin Count
16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
558G-01LF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS558G-01LF
Manufacturer:
IDT
Quantity:
20 000
PECL/CMOS TO CMOS CLOCK DRIVER
Description
The ICS558-01 accepts a high speed input of either PECL
or CMOS, integrates a divider of 1, 2, 3, or 4, and provides
four CMOS low skew outputs. The chip also has output
enables so that one, three, or all four outputs can be
tri-stated.
The ICS558-01 is a member of the IDT Clock Blocks™ family
of clock generation, synchronization, and distribution
devices.
Block Diagram
IDT™ / ICS™ PECL/CMOS TO CMOS CLOCK DRIVER
SELPECL
CMOSIN
PECLIN
PECLIN
S0, S1
2
1
0
Output Divide
VDDP
GND
1
Features
16-pin TSSOP package
Pb (lead) free package
Selectable PECL or CMOS inputs
Operates up to 250 MHz
Works as a voltage translator
Four low skew (<250 ps) outputs
Selectable internal divider
Operating input voltages of 3.3 V or 5.0 V
Operating output voltages of 2.5 V, 3.3 V or 5.0 V
Ideal for IA64 designs
GND
VDDC
OE1
OE0
ICS558-01
DATASHEET
CLK1
CLK2
CLK3
CLK4
ICS558-01
REV F 051310

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ICS558G-01LF Summary of contents

Page 1

PECL/CMOS TO CMOS CLOCK DRIVER Description The ICS558-01 accepts a high speed input of either PECL or CMOS, integrates a divider and provides four CMOS low skew outputs. The chip also has output enables ...

Page 2

ICS558-01 PECL/CMOS TO CMOS CLOCK DRIVER Pin Assignment VDDP 3 PECLIN 4 PECLIN 5 GND 6 CMOSIN 7 OE0 8 16-pin 173 Mil (0.65mm) TSSOP Pin Descriptions Pin Pin Pin Type Number Name 1 S0 Input ...

Page 3

ICS558-01 PECL/CMOS TO CMOS CLOCK DRIVER External Components The ICS558-01 requires two 0.01 of the chip. These must be close to the chip to minimize lead inductance. Series termination resistors of 33Ω can be used on the outputs (these also ...

Page 4

ICS558-01 PECL/CMOS TO CMOS CLOCK DRIVER Parameter Output High Voltage Output Low Voltage Operating Supply Current Operating Supply Current Short Circuit Current On-chip pull-up resistor Input Capacitance AC Electrical Characteristics VDDP = VDDC = 3.3 V (unless stated otherwise), Ambient ...

Page 5

ICS558-01 PECL/CMOS TO CMOS CLOCK DRIVER Package Outline and Package Dimensions Package dimensions are kept current with JEDEC Publication No. 95, MO-153 16 INDEX AREA Ordering Information Part / Order Number Marking 558G-01LF 558G-01LF ...

Page 6

ICS558-01 PECL/CMOS TO CMOS CLOCK DRIVER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications ...

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