IDT85304-01PGG IDT, Integrated Device Technology Inc, IDT85304-01PGG Datasheet - Page 2

• Manufacturer Part Number: IDT85304-01PGG
• Description: IC CLK FAN BUFF MUX 1:5 20TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of IDT85304-01PGG

• Number Of Circuits: 1
• Ratio - Input:output: 1:5
• Differential - Input:output: Yes/Yes
• Input: CML, HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVPECL
• Frequency - Max: 650MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 650MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 85304-01PGG

PIN CONFIGURATION
PIN DESCRIPTION
NOTE:
1. Pullup and Pulldown refer to internal input resistors. See Capacitance table for typical values.
IDT85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
CLK_SEL
CLK_EN
xQ0, Q0
xQ1, Q1
xQ2, Q2
xQ3, Q3
xQ4, Q4
Symbol
xPCLK
xCLK
PCLK
CLK
V
V
DD
EE
xQ0
xQ1
xQ2
xQ3
xQ4
Q0
Q1
Q2
Q3
Q4
Number
11, 18, 20
9, 10
1, 2
3, 4
5, 6
7, 8
12
13
14
15
16
17
19
1
2
3
4
5
6
7
8
9
10
TOP VIEW
TSSOP
(1)
Power
Power
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
20
19
18
17
16
15
14
13
12
11
Type
V
CLK_EN
V
xPCLK
PCLK
V
xCLK
CLK
CLK_SEL
V
Pulldown
Pulldown
Pulldown
EE
DD
DD
DD
Pullup
Pullup
Pullup
2
ABSOLUTE MAXIMUM RATINGS
CAPACITANCE
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
Parameter
R
Symbol
V
V
V
θ
T
Differential Output Pair. LVPECL interface levels.
Differential Output Pair. LVPECL interface levels.
Differential Output Pair. LVPECL interface levels.
Differential Output Pair. LVPECL interface levels.
Differential Output Pair. LVPECL interface levels.
Positive Supply Pins
CLK / xCLK inputs. LVTTL / LVCMOS interface levels.
Inverting Differential Clock Input
Negative Supply Pin
Non-Inverting Differential LVPECL Clock Input
Inverting Differential LVPECL Clock Input
Synchronizing Clock Enable. When HIGH, clock outputs follow clock input. When
LOW, Q outputs are forced LOW, xQ outputs are forced HIGH. LVTTL / LVCMOS
interface levels.
Clock Select Input. When HIGH, selects PCLK / xPCLK inputs. When LOW, selects
Non-Inverting Differential Clock Input
R
PULLDOWN
STG
DD
I
O
JA
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
PULLUP
C
IN
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Power Supply Voltage
Input Voltage
Output Voltage
Package Thermal Impedance (0 lfpm)
Storage Temperature
Description
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Description
(T
A
= +25°C, f = 1MHz, V
Description
–0.5 to V
–0.5 to V
Typ.
—
51
51
–65 to +150
IN
= 0V)
Max
92.6
4.6
DD
DD
Max.
—
—
4
(1)
+0.5
+0.5
°C/W
Unit
Unit
K Ω
KΩ
° C
pF
V
V
V