ICS83948AYI-147LFT IDT, Integrated Device Technology Inc, ICS83948AYI-147LFT Datasheet - Page 7

• Manufacturer Part Number: ICS83948AYI-147LFT
• Description: IC FANOUT BUFFER 1:12 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of ICS83948AYI-147LFT

• Number Of Circuits: 1
• Ratio - Input:output: 2:12
• Differential - Input:output: Yes/No
• Input: HCSL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL, SSTL
• Output: LVCMOS, LVTTL
• Frequency - Max: 350MHz
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 350MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 83948AYI-147LFT

Table 5C. AC Characteristics, V
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to V
NOTE 2: Measured from V
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at V
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR
Parameter
f
t
tjit
tsk(o)
tsk(pp)
t
odc
t
t
t
t
MAX
PD
R
PZL,
PLZ,
S
H
ICS83948I-147
LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
/ t
F
t
t
PZH
PHZ
Symbol
Output Frequency
Propagation Delay
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
Output Skew; NOTE 3, 7
Part-to-Part Skew; NOTE 4, 7
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
Clock Enable
Setup Time;
NOTE 6
Clock Enable
Hold Time;
NOTE 6
DD
/2 of the input to V
CLK/nCLK; NOTE 1
LVCMOS_CLK;
NOTE 2
CLK_EN to CLK/nCLK
CLK_EN to
LVCMOS_CLK
CLK/nCLK to CLK_EN
LVCMOS_CLK to
CLK_EN
DD
= 3.3V ± 5%, V
DDO
/2 of the output.
DDO
ƒ ≤ 200MHz, Ref = CLK/nCLK
Measured on the Rising Edge
Measured on the Rising Edge
= 2.5V ± 5%, T
DDO
7
Integration Range:
/2 of the output.
Test Conditions
12kHz – 20MHz
ƒ ≤ 350MHz
ƒ ≤ 350MHz
155.52MHz,
0.8V to 2V
@ V
@ V
DDO
DDO
DDO
/2.
A
/2
/2
= -40°C to 85°C
Minimum Typical Maximum Units
0.1
45
ICS83948AYI-147 REV. D APRIL 8, 2009
2
2
1
0
0
1
0.14
DDO
350
100
1.0
55
4
4
1
1
5
5
/2.
MHz
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%