ICS8308AGILF IDT, Integrated Device Technology Inc, ICS8308AGILF Datasheet - Page 10

• Manufacturer Part Number: ICS8308AGILF
• Description: IC CLK BUFFER 1:8 350MHZ 24TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Fanout Buffer (Distribution), Multiplexerr
• Series: HiPerClockS™r

Specifications of ICS8308AGILF

• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: Yes/No
• Input: HCSL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL, SSTL
• Output: LVCMOS, LVTTL
• Frequency - Max: 350MHz
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Frequency-max: 350MHz
• Number Of Clock Inputs: 2
• Output Frequency: 350MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 8308AGILF

ICS8308I Data Sheet
W
Figure 1 shows how a differential input can be wired to accept
single ended levels. The reference voltage V
by the bias resistors R1 and R2. The bypass capacitor (C1) is
used to help filter noise on the DC bias. This bias circuit should
be located as close to the input pin as possible. The ratio of R1
and R2 might need to be adjusted to position the V
center of the input voltage swing. For example, if the input clock
swing is 2.5V and V
to set V
ended swing and V
requires that the sum of the output impedance of the driver (Ro)
and the series resistance (Rs) equals the transmission line
impedance. In addition, matched termination at the input will
attenuate the signal in half. This can be done in one of two ways.
First, R3 and R4 in parallel should equal the transmission line
ICS8308AGI REVISION C MARCH 23, 2011
IRING THE
REF
at 1.25V. The values below are for when both the single-
D
IFFERENTIAL
F
IGURE
DD
DD
= 3.3V, R1 and R2 value should be adjusted
are at the same voltage. This configuration
1. R
ECOMMENDED
I
NPUT TO
A
S
REF
CCEPT
CHEMATIC FOR
A
= V
PPLICATION
DD
/2 is generated
S
INGLE
REF
W
in the
IRING A
E
NDED
10
D
LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
I
IFFERENTIAL
L
NFORMATION
impedance. For most 50 applications, R3 and R4 can be 100 .
The values of the resistors can be increased to reduce the loading
for slower and weaker LVCMOS driver. When using single ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however V
than -0.3V and V
the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
EVELS
I
NPUT TO
IH
cannot be more than V
A
CCEPT
S
INGLE
-
2011 Integrated Device Technology, Inc.
ENDED
DD
L
+ 0.3V. Though some of
EVELS
IL
cannot be less