ICS8533AGI-01LFT IDT, Integrated Device Technology Inc, ICS8533AGI-01LFT Datasheet - Page 6

• Manufacturer Part Number: ICS8533AGI-01LFT
• Description: IC FANOUT BUFFER 1-4 20-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Fanout Buffer (Distribution), Multiplexerr
• Series: HiPerClockS™r

Specifications of ICS8533AGI-01LFT

• Number Of Circuits: 1
• Ratio - Input:output: 2:4
• Differential - Input:output: Yes/Yes
• Input: CML, HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVPECL
• Frequency - Max: 650MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 650MHz
• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 650MHz
• Output Logic Level: LVPECL
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 8533AGI-01LFT

8533AGI-01
The spectral purity in a band at a specific offset from the fun-
damental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using
a Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the
fundamental frequency to the power value of the fundamental.
This ratio is expressed in decibels (dBm) or a ratio of the power
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher
than the noise floor of the device. This is illustrated above. The
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-10
-20
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-50
-60
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0
1k
10k
A
O
DDITIVE
FFSET
100k
F
D
ROM
IFFERENTIAL
P
C
HASE
6
ARRIER
in the 1Hz band to the power in the fundamental. When the
required offset is specified, the phase noise is called a dBc
value, which simply means dBm at a specified offset from the
fundamental. By investigating jitter in the frequency domain,
we get a better understanding of its effects on the desired ap-
plication over the entire time record of the signal. It is math-
ematically possible to calculate an expected bit error rate given
a phase noise plot.
device meets the noise floor of what is shown, but can actually
be lower. The phase noise is dependent on the input source
and measurement equipment.
J
F
ITTER
REQUENCY
-
TO
1M
-3.3V LVPECL F
(H
Z
)
Phase Jitter
Input/Output Additive
ICS8533I-01
10M
L
= 0.060ps (typical)
OW
ANOUT
at 156.25MHz
S
REV. A DECEMBER 6, 2007
KEW
, 1-
B
UFFER
TO
100M
-4