ICS85310AYI-21LNT IDT, Integrated Device Technology Inc, ICS85310AYI-21LNT Datasheet - Page 5
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ICS85310AYI-21LNT
Manufacturer Part Number
ICS85310AYI-21LNT
Description
IC FANOUT BUFFER 1-5 DUAL 32LQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Fanout Buffer (Distribution)r
Datasheet
1.ICS85310AYI-21LNT.pdf
(16 pages)
Specifications of ICS85310AYI-21LNT
Number Of Circuits
2
Ratio - Input:output
1:5
Differential - Input:output
Yes/Yes
Input
HCSL, LVDS, LVHSTL, LVPECL, SSTL
Output
ECL, LVPECL
Frequency - Max
700MHz
Voltage - Supply
2.375 V ~ 3.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-LQFP
Frequency-max
700MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
85310AYI-21LNT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICS85310AYI-21LNT
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
85310AYI-21
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0
100
1k
D
IFFERENTIAL
10k
A
O
FFSET
DDITIVE
F
-
www.idt.com
ROM
TO
P
-2.5V/3.3V ECL/LVPECL F
100k
C
HASE
5
ARRIER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
J
F
ITTER
REQUENCY
1M
@ 155.52MHz = <0.13ps typical
Additive Phase Jitter, RMS
(H
Z
)
L
OW
ICS85310I-21
S
10M
KEW
, D
ANOUT
REV. E AUGUST 13, 2010
UAL
100M
, 1-
B
UFFER
TO
-5