ICS85310AYI-21LNT IDT, Integrated Device Technology Inc, ICS85310AYI-21LNT Datasheet
ICS85310AYI-21LNT
Specifications of ICS85310AYI-21LNT
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ICS85310AYI-21LNT Summary of contents
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ENERAL ESCRIPTION The ICS85310I- low skew, high perfor- mance dual 1-to-5 Differential-to-2.5V/3.3VECL/LVPECL Fanout Buffer. The CLKx, nCLKxpairs can accept most standard differential input levels.The ICS85310I-21 is characterized to operate from either a 2. ...
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ABLE IN ESCRIPTIONS ...
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BSOLUTE AXIMUM ATINGS Supply Voltage, V 4.6V CC Negative Supply Voltage, V -4.6V EE Inputs, V -0. Outputs Continuous Current 50mA Surge Current 100mA Operating Temperature Range, TA -40°C to +85°C ...
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ABLE HARACTERISTICS ...
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D The spectral purity in a band at a specific offset from the funda- mental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is ...
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D P ARAMETER CCO LVPECL V EE -0.375V to -1.8V 3. UTPUT OAD EST IRCUIT nQx PART 1 Qx nQy PART 2 Qy tsk(pp ART TO ...
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IRING THE IFFERENTIAL NPUT TO Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ V generated by the bias resistors R1, R2 and C1. This ...
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D T 2.5V LVPECL O ERMINATION FOR Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminat- ing 50Ω 2V. For V = 2.5V, the ...
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IFFERENTIAL LOCK NPUT NTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING the V and V input requirements. Figures show PP CMR interface examples ...
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D This section provides information on power dissipation and junction temperature for the ICS85310I-21. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85310I-21 is the sum of the core power plus the ...
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D 3. Calculations and Equations. LVPECL output driver circuit and termination are shown in Figure 5. F IGURE T o calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination ...
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D θ ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second ...
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ACKAGE UTLINE UFFIX FOR ABLE ...
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ABLE RDERING NFORMATION ...
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D We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks ...