MC100LVEL37DWG ON Semiconductor, MC100LVEL37DWG Datasheet - Page 2

• Manufacturer Part Number: MC100LVEL37DWG
• Description: IC BUFFER FANOUT ECL 1:4 20SOIC
• Manufacturer: ON Semiconductor
• Series: 100LVELr
• Type: Fanout Buffer (Distribution), Divider, Multiplexerr

Specifications of MC100LVEL37DWG

• Number Of Circuits: 1
• Ratio - Input:output: 2:4
• Differential - Input:output: Yes/Yes
• Input: ECL
• Output: ECL
• Frequency - Max: 1GHz
• Voltage - Supply: 3 V ~ 3.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Frequency-max: 1GHz
• Output Logic Level: ECL
• Supply Voltage (max): +/- 3.8 V
• Supply Voltage (min): +/- 3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Multiply / Divide Factor: 2:1
• Number Of Clock Inputs: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MC100LVEL37DWGOS

Table 3. MAXIMUM RATINGS
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may
affect device reliability.
V
V
V
I
T
T
q
q
T
Symbol
out
A
stg
JA
JC
sol
CC
EE
I
V
V
Warning: All V
to Power Supply to guarantee proper operation.
20
EE
1
CC
V
Q0
19
Figure 1. 20−Lead Pinout (Top View)
2
CC
PECL Mode Power Supply
NECL Mode Power Supply
PECL Mode Input Voltage
NECL Mode Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction to Ambient)
Thermal Resistance (Junction to Case)
Wave Solder
CLK0 CLK0 Clk_Sel CLK1 CLK1
Q0
18
3
CC
and V
Q1
17
4
EE
Parameter
Q1
16
5
pins must be externally connected
÷1 ÷2
Q2
15
6
Q2
14
7
Pb−Free
MR
Q3
13
8
Pb
V
Q3
12
9
EE
http://onsemi.com
V
V
V
V
Continuous
Surge
0 lfpm
500 lfpm
Standard Board
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
EE
CC
EE
CC
V
V
11
10
CC
EE
Condition 1
= 0 V
= 0 V
= 0 V
= 0 V
2
Table 1. TRUTH TABLE
Table 2. PIN DESCRIPTION
PIN
Q0, Q0; Q1, Q1
Q2, Q2; Q3, Q3
CLKn, CLKn
Clk_Sel
MR
V
V
X = Don’t Care
Clk_Sel
CC
EE
H
X
L
V
V
20 SOIC
20 SOIC
20 SOIC
I
I
 V
 V
Condition 2
CC
EE
MR
H
L
L
FUNCTION
ECL Differential Clock ÷1 Outputs
ECL Differential Clock ÷2 Outputs
ECL Differential Clock Inputs
ECL Input Clock Selection
ECL Asynchronous Master Reset
Positive Supply
Negative Supply
CLK0/÷1
CLK1/÷1
Q0, 1
L
−65 to +150
−40 to +85
30 to 35
Rating
−8 to 0
−6 to 0
8 to 0
6 to 0
100
265
265
50
90
60
CLK0/÷2
CLK1/÷2
Q2, 3
L
°C/W
°C/W
°C/W
Unit
mA
mA
°C
°C
°C
V
V
V
V