MC100LVEL37DWG ON Semiconductor, MC100LVEL37DWG Datasheet - Page 4

• Manufacturer Part Number: MC100LVEL37DWG
• Description: IC BUFFER FANOUT ECL 1:4 20SOIC
• Manufacturer: ON Semiconductor
• Series: 100LVELr
• Type: Fanout Buffer (Distribution), Divider, Multiplexerr

Specifications of MC100LVEL37DWG

• Number Of Circuits: 1
• Ratio - Input:output: 2:4
• Differential - Input:output: Yes/Yes
• Input: ECL
• Output: ECL
• Frequency - Max: 1GHz
• Voltage - Supply: 3 V ~ 3.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Frequency-max: 1GHz
• Output Logic Level: ECL
• Supply Voltage (max): +/- 3.8 V
• Supply Voltage (min): +/- 3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Multiply / Divide Factor: 2:1
• Number Of Clock Inputs: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MC100LVEL37DWGOS

Table 6. AC CHARACTERISTICS
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
7. V
8. Within-device skew defined as identical transitions on similar paths through a device.
9. Duty cycle skew is the difference between a TPLH and TPHL propagation delay through a device.
10. V
Symbol
fmax
t
t
t
t
V
t
t
PLH
PHL
SKEW
JITTER
r
f
PP
PP
EE
(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40.
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
can vary ±0.3 V.
Propagation Delay
Input Swing (Note 10)
Output Rise/Fall Times Q
(20% − 80%)
Maximum Toggle Frequency
Within-Device Skew (Note 8)
Duty Cycle Skew (Differential Configuration)
(Note 9)
Cycle−to−Cycle Jitter
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Figure 2. Typical Termination for Output Driver and Device Evaluation
Driver
Device
Characteristic
V
CC
Q
Q
CLK to Q/Q (Diff)
= 3.3 V; V
CLK to Q/Q
MR to Q
EE
= 0.0 V or V
Z
Z
http://onsemi.com
o
o
= 50 W
= 50 W
Min
640
620
640
150
280
50 W
V
4
CC
TT
−40°C
= 0.0 V; V
TBD
TBD
= V
Typ
V
CC
TT
− 2.0 V
1000
Max
940
920
920
550
50
50
50 W
EE
= −3.3 V (Note 7)
Min
680
680
680
150
280
25°C
TBD
TBD
Typ
D
D
700
700
700
1000
Max
920
940
920
550
Receiver
Device
50
50
Min
720
720
720
150
280
85°C
TBD
TBD
Typ
1000
Max
980
970
980
550
50
50
GHz
Unit
mV
ps
ps
ps
ps