PCK9446BD,128 NXP Semiconductors, PCK9446BD,128 Datasheet - Page 11

• Manufacturer Part Number: PCK9446BD,128
• Description: IC CLOCK BUFFER FANOUT 32LQFP
• Manufacturer: NXP Semiconductors
• Type: Fanout Buffer (Distribution), Divider, Multiplexerr

Specifications of PCK9446BD,128

• Number Of Circuits: 1
• Ratio - Input:output: 2:10
• Differential - Input:output: No/No
• Input: LVCMOS
• Output: LVCMOS
• Frequency - Max: 250MHz
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 250MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935280839128; PCK9446BD-F; PCK9446BD-F

Philips Semiconductors
12. Test information
PCK9446_1
Product data sheet
Fig 6. CLK0, CLK1 PCK9446 AC test reference for V
Fig 7. Output transition time test reference
Fig 9. Propagation delay (t
(1) 2.4 V when V
(2) 0.55 V when V
CLK0, CLK1
Qn
t
f
CC
CC
t
= 3.3 V; 1.8 V when V
PD
= 3.3 V; 0.6 V when V
Fig 5. Optimized dual line termination
PD
GENERATOR
t
r
) test reference
Z = 50
PULSE
14
25
002aab292
+ 22
= 25
(2)
(1)
CC
CC
002aaa712
= 2.5 V.
22
= 2.5 V.
Z o = 50
V
0.5V
GND
V
0.5V
GND
CC
CC
Rev. 01 — 10 April 2006
IN
R T = 50
= 50
CC
CC
CC
V
T
PCK9446
50
OUTPUT
BUFFER
= 3.3 V and V
Fig 8. Output duty cycle (
Fig 10. Output skew time (t
PCK9446
D.U.T.
14
R o
2.5 V and 3.3 V LVCMOS clock fan-out buffer
The time from the PLL controlled edge to the
non-controlled edge, divided by the time between
PLL controlled edges, expressed as a percentage.
The pin-to-pin skew is defined as the worst case
difference in a propagation delay between any
similar delay path within a single device.
R s = 22
R s = 22
CC
o
Z o = 50
= (t
= 2.5 V
p
t
sk(o)
T
R T = 50
Z o = 50
Z o = 50
Z o = 50
o
t
p
002aaa710
100 %)
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
T
002aaa709
V
o
T
sk(o)
o
)
)
PCK9446
002aab291
t
sk(o)
V
0.5V
GND
CC
002aab289
CC
V
0.5V
GND
V
0.5V
GND
CC
CC
CC
CC
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