MPC9443AE Freescale Semiconductor, MPC9443AE Datasheet - Page 8

• Manufacturer Part Number: MPC9443AE
• Description: IC CLOCK FANOUT BUFF LV 48-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Fanout Buffer (Distribution), Divider, Multiplexerr

Specifications of MPC9443AE

• Number Of Circuits: 1
• Ratio - Input:output: 2:16
• Differential - Input:output: Yes/No
• Input: LVCMOS, LVPECL
• Output: LVCMOS
• Frequency - Max: 350MHz
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Frequency-max: 350MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MOTOROLA
Driving Transmission Lines
signals in a terminated transmission line environment. To
provide the optimum flexibility to the user the output drivers
were designed to exhibit the lowest impedance possible. With
an output impedance of less than 20 Ω the drivers can drive
either parallel or series terminated transmission lines at
V
reader is referred to application note AN1091. In most high
performance clock networks point-to-point distribution of
signals is the method of choice. In a point-to-point scheme
either series terminated or parallel terminated transmission
lines can be used. The parallel technique terminates the signal
at the end of the line with a 50 Ω resistance to V
thus only a single terminated line can be driven by each output
of the MPC9443 clock driver. For the series terminated case
however there is no DC current draw, thus the outputs can drive
multiple series terminated lines. Figure 3 . Single versus Dual
Transmission Lines illustrates an output driving a single series
terminated line versus two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC9443 clock
driver is effectively doubled due to its capability to drive multiple
lines (at V
Waveforms show the simulation results of an output driving a
single line versus two lines. In both cases the drive capability of
the MPC9443 output buffer is more than sufficient to drive 50 Ω
transmission lines on the incident edge. Note from the delay
measurements in the simulations a delta of only 43 ps exists
between the two differently loaded outputs. This suggests that
the dual line driving need not be used exclusively to maintain
the tight output-to-output skew of the MPC9443. The output
waveform in Figure 4. Single versus Dual Waveforms shows
a step in the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel combination
MPC9443
CC
The MPC9443 clock driver was designed to drive high speed
This technique draws a fairly high level of DC current and
The waveform plots in Figure 4. Single versus Dual
IN
IN
= 3.3 V. For more information on transmission lines the
Figure 3. Single versus Dual Transmission Lines
CC
MPC9443
MPC9443
OUTPUT
OUTPUT
BUFFER
BUFFER
19Ω
19Ω
= 3.3 V).
R
R
R
S
S
S
= 31 Ω
= 31 Ω
= 31 Ω
Z
Z
Z
O
O
O
= 50 Ω
= 50 Ω
= 50 Ω
APPLICATIONS INFORMATION
CC
÷2.
OutA
OutB0
OutB1
8
of the 31 Ω series resistor plus the output impedance does not
match the parallel combination of the line impedances. The
voltage wave launched down the two lines will equal:
reflection coefficient, to 2.52 V. It will then increment towards
the quiescent 3.0 V in steps separated by one round trip delay
(in this case 4.0 ns).
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the situation
in Figure 5. Optimized Dual Line Termination should be
used. In this case the series terminating resistors are reduced
such that when the parallel combination is added to the output
buffer impedance the line impedance is perfectly matched.
At the load end the voltage will double, due to the near unity
Since this step is well above the threshold region it will not
3.0
2.5
2.0
1.5
1.0
0.5
0
Figure 5. Optimized Dual Line Termination
Figure 4. Single versus Dual Waveforms
MPC9443
OUTPUT
BUFFER
t
19Ω
V
Z
R
R
V
D
2
0
L
L
S
0
= 3.8956
19Ω + 12Ω || 12Ω = 50Ω || 50Ω
OutA
In
= 50 Ω || 50 Ω
= V
= 3.0 (25 ÷ (15.5 + 19 + 25)
= 19 Ω
= 31 Ω || 31 Ω
= 1.26V
S
4
(Z
0
25Ω = 25Ω
÷ (R
R
R
S
S
6
= 12 Ω
= 12 Ω
TIME (ns)
S
t
D
+ R
= 3.9386
OutB
8
0
+ Z
Z
Z
O
O
0
= 50 Ω
= 50 Ω
))
10
TIMING SOLUTIONS
12
14