MC100LVE210FN ON Semiconductor, MC100LVE210FN Datasheet

MC100LVE210FN

Manufacturer Part Number

MC100LVE210FN

Description

IC BUFFER FANOUT DUAL DFF 28PLCC

Manufacturer

ON Semiconductor

Series

100LVEr

Type

Fanout Buffer (Distribution)r

Datasheet

1.MC100LVE210FNR2G.pdf (8 pages)

Specifications of MC100LVE210FN

Number Of Circuits

Ratio - Input:output

1:4, 1:5

Differential - Input:output

Yes/Yes

Input

ECL, PECL

Output

ECL, PECL

Frequency - Max

700GHz

Voltage - Supply

3 V ~ 3.8 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

28-PLCC

Frequency-max

700GHz

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

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Part Number:

MC100LVE210FNR2

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MC100LVE210FNR2G

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MC100LVE210

3.3V ECL Dual 1:4, 1:5

Differential Fanout Buffer

Description

fanout buffer designed with clock distribution in mind. The device features

two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device

features fully differential clock paths to minimize both device and system

skew. The dual buffer allows for the fanout of two signals through a single

chip, thus reducing the skew between the two fundamental signals from a

part−to−part skew down to an output−to−output skew. This capability

reduces the skew by a factor of 4 as compared to using two LVE111’s to

accomplish the same task.

sides of the differential output are identically terminated, even if only one

side is being used. In most applications all nine differential pairs will be

used and therefore terminated. In the case where fewer than nine pairs are

used it is necessary to terminate at least the output pairs adjacent to the

output pair being used in order to maintain minimum skew. Failure to

follow this guideline will result in small degradations of propagation delay

(on the order of 10−20 ps) of the outputs being used, while not catastrophic

to most designs this will result in an increase in skew. Note that the

package corners isolate outputs from one another such that the guideline

expressed above holds only for outputs on the same side of the package.

positive V

for high performance clock distribution in +3.3 V systems. Designers can

take advantage of the LVE210’s performance to distribute low skew clocks

across the backplane or the board. In a PECL environment series or

Thevenin line terminations are typically used as they require no additional

power supplies, if parallel termination is desired a terminating voltage of

PECL, designers should refer to Application Note AN1406/D.

device only. For single-ended input conditions, the unused differential

input is connected to V

rebias AC coupled inputs. When used, decouple V

0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When

not used, V

Features

•

*For additional information on our Pb−Free strategy and soldering details, please

December, 2006 − Rev. 7

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

The MC100LVE210 is a low voltage, low skew dual differential ECL

To ensure that the tight skew specification is met it is necessary that both

The MC100LVE210, as with most ECL devices, can be operated from a

The V

NECL Mode Operating Range: V

200 ps Part−to−Part Skew

50 ps Typical Output−to−Output Skew

The 100 Series Contains Temperature Compensation

PECL Mode Operating Range: V

Internal Input Pulldown Resistors

Q Output will Default LOW with Inputs Open or at V

Pb−Free Packages are Available*

− 2.0 V will need to be provided. For more information on using

pin, an internally generated voltage supply, is available to this

supply in PECL mode. This allows the LVE210 to be used

should be left open.

as a switching reference voltage. V

= 0 V with V

= 3.0 V to 3.8 V with V

= −3.0 V to −3.8 V

and V

may also

via a

= 0 V

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

*For additional marking information, refer to

Application Note AND8002/D.

FN SUFFIX

CASE 776

PLCC−28

ORDERING INFORMATION

http://onsemi.com

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

Publication Order Number:

MC100LVE210G

DIAGRAM*

MC100LVE210/D

MARKING

AWLYYWW

1 28

Related parts for MC100LVE210FN

MC100LVE210FN Summary of contents

Page 1

... Q Output will Default LOW with Inputs Open • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 December, 2006 − Rev. 7 ...

Page 2

Qa0 Qa0 Qa1 V Qa1 Qa2 Qa2 CCO CLKa Pinout: 28−Lead PLCC (Top View) CLKa 2 3 CLKb CLKb Qb4 ...

Page 3

Table 3. MAXIMUM RATINGS Symbol Parameter V PECL Mode Power Supply CC V NECL Mode Power Supply EE V PECL Mode Input Voltage I NECL Mode Input Voltage I Output Current out I V Sink/Source Operating Temperature ...

Page 4

Table 4. LVPECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended Output ...

Page 5

Table 6. AC CHARACTERISTICS V CC Symbol Characteristic f Maximum Toggle Frequency max t Propagation Delay to Output PLH t IN (Differential) (Note 9) PHL IN (Single−Ended) (Note 10) t Within−Device Skew (Note 11) skew ...

Page 6

... Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC100LVE210FN MC100LVE210FNG MC100LVE210FNR2 MC100LVE210FNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D ...

Page 7

0.010 (0.250) T L− NOTES: 1. DATUMS −L−, −M−, AND −N− DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT ...

Page 8

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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