ADF4113HVBRUZ Analog Devices Inc, ADF4113HVBRUZ Datasheet - Page 13

• Manufacturer Part Number: ADF4113HVBRUZ
• Description: IC CHARGE PUMP HV SYNTH 16-TSSOP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of ADF4113HVBRUZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 4GHz
• Pll Type: Frequency Synthesis
• Frequency: 4GHz
• Supply Current: 16mA
• Supply Voltage Range: 2.7V To 5.5V
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4113HVEB1Z - BOARD EVALUATION FOR ADF4113HVEVAL-ADF4113EBZ2 - BOARD EVAL FOR ADF4113 1750MHZEVAL-ADF4113EBZ1 - BOARD EVAL FOR ADF4113EVAL-ADF411XEBZ1 - BOARD EVAL FOR ADF411X NO CHIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Function Latch Map
FUNCTION LATCH
The on-chip function latch is programmed with C2 and C1 set
to 1,0, respectively. Figure 22 shows the input data format for
programming the function latch.
Counter Reset
DB2 (F1) is the counter reset bit. When DB2 is 1, the R counter
and the AB counters are reset. For normal operation, this bit
should be 0. Upon powering up, the F1 bit must be disabled,
and the N counter resumes counting in close alignment with
the R counter. (The maximum error is one prescaler cycle.)
Power-Down
DB3 (F2) in the function latch provides a software power-down
for the ADF4113HV. The device powers down immediately
after latching a 1 into Bit F2.
When the CE pin is low, the device immediately powers down
regardless of the state of the power-down bit (F2).
When a power-down is activated (either through software or
a CE pin activated power-down), the following events occur:
•
•
•
•
All active dc current paths are removed.
The R, N, and timeout counters are forced to their load
state conditions.
The charge pump is forced into three-state mode.
The digital clock detect circuitry is reset.
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P2
0
0
1
1
SCALER
P2
VALUE
PRE-
P1
P1
0
1
0
1
PRESCALER VALUE
8/9
16/17
32/33
64/65
0
RESERVED
0
0
CPI3
0
1
0
CPI2
0
1
CP3
CURRENT
SETTING
CP2
CPI1
0
1
CP1
I
4.7kΩ
80
640
CP
0
(µA)
Figure 22. Function Latch Map
0
Rev. A | Page 13 of 20
RESERVED
0
F4
0
1
0
F3
1
0
CHARGE PUMP
OUTPUT
NORMAL
THREE-STATE
0
•
•
•
MUXOUT Control
The on-chip multiplexer is controlled by M3, M2, and M1 on
the ADF4113HV. Figure 22 shows the truth table.
Charge Pump Currents
CPI3, CPI2, and CPI1 program the current setting for the
charge pump. The truth table is given in Figure 22.
Prescaler Value
P2 and P1 in the function latch set the prescaler values. The
prescaler value should be chosen so that the prescaler output
frequency is always less than or equal to 200 MHz. Thus, with
an RF frequency of 2 GHz, a prescaler value of 16/17 is valid,
but a value of 8/9 is not.
PD Polarity
This bit sets the phase detector polarity bit. See Figure 22.
CP Three-State
This bit controls the CP output pin. With the bit set high, the
CP output is put into three-state. With the bit set low, the CP
output is enabled.
PHASE DETECTOR
POLARITY
POSITIVE
NEGATIVE
0
The RF
The reference input buffer circuitry is disabled.
The input register remains active and capable of loading
and latching data.
M3
0
0
0
0
1
1
1
1
F4
M2
0
0
1
1
0
0
1
1
F3
IN
A and RF
M1
0
1
0
1
0
1
0
1
M3
CONTROL
MUXOUT
OUTPUT
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
DV
R DIVIDER OUTPUT
ANALOG LOCK DETECT
SERIAL DATA OUTPUT
DGND
M2
IN
DD
B inputs are debiased.
M1
PD1
0
1
F2
F1
F1
0
1
OPERATION
NORMAL
POWER DOWN
C2(1) C1(0)
CONTROL
COUNTER
OPERATION
NORMAL
R, A, B COUNTERS
HELD IN RESET
BITS
ADF4113HV