LMX2541SQE2060E/NOPB National Semiconductor, LMX2541SQE2060E/NOPB Datasheet - Page 45

• Manufacturer Part Number: LMX2541SQE2060E/NOPB
• Description: IC PLL FREQ SYNTH W/VCO 36LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of LMX2541SQE2060E/NOPB

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 2.24GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-LLP
• Frequency-max: 2.24GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMX2541SQE2060ETR

MUX[3:0] -- Multiplexed Output for Ftest/LD Pin
The MUX[3:0] word is used to program the output of the Ftest/LD Pin. This pin can be used for a general purpose I/O pin, a lock
detect pin, and for diagnostic purposes. When programmed to the digital lock detect state, the output of the Ftest/LD pin will be
high when the device is in lock, and low otherwise. The output voltage level of the Ftest/LD is not equal to the supply voltage of
the device, but rather is given by V
Because the Ftest/LD pin is close to the OSCin pin, the state of this pin can have an impact on the performance of the device. If
any of the diagnostic modes (8-13) are used, the OSCin sensitivity can be severely degraded, so these should only be used for
diagnostic purposes. The fractional spurs can also be impacted a little by the MUX programming word. The Push-Pull digital lock
detect modes, like mode 3, tend to have the best fractional spurs, so these states are recommended, even if the digital lock detect
function is not needed.
CPP - Charge Pump Polarity
This bit sets the polarity of the phase detector.
OSC2X-- OSCin Frequency Doubler
Enabling this bit doubles the OSCin frequency. This is useful in achieving a higher phase detector frequency to improve PLL phase
noise, push out noise from the delta sigma modulator, and sometimes reduce fractional spurs . Note that when this bit is enabled,
the R divider is bypassed.
FDM - Extended Fractional Denominator Mode Enable
Enabling this bit allows the fractional numerator and denominator to be expanded from 10 bits to 22 bits. In 10-bit mode, only the
first 10 bits of the fractional numerator and denominator are considered. When using FSK mode, this bit has to be disabled.
14-15
MUX
10
11
12
13
0
1
2
3
4
5
6
7
8
9
CPP
0
1
High Impedance
Output Type
Open Drain
Open Drain
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
N/A
OH
Charge Pump Polarity
and V
1 (Default)
OSC_2X
Inverse Digital Lock Detect
Negative
OL
Positive
FDM
0
1
0
in the electrical characteristics specification.
Analog Lock Detect
Analog Lock Detect
Digital Lock Detect
Digital Lock Detect
Logical High State
Logical Low State
N Divider / 2
R Divider / 2
PFD Down
Function
Reserved
N Divider
R Divider
Disabled
PFD Up
45
OSCin frequency is doubled
External VCO Mode with an inverting active loop filter.
Fractional Mode
divider, R divider, and phase frequency detector (PFD)
External VCO Mode with a passive loop filter.
use of these modes (including R Divider) can degrade
output is divided by 2, there is a 50% duty cycle. The
Typically, the output is narrow pulses, but when the
These allow the user to view the outputs of the N
Consult Functional Description for more details
and are intended only for diagnostic purposes.
Normal
State 3 is recommended for optimal spurious
10-bit
22-bit
State
Typical Applications
General Purpose I/O Modes
Full Chip Mode
the OSCin sensitivity.
Lock Detect Modes
Diagnostic Modes
performance.
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